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參數(shù)資料
| 型號： | W132-10BX |
| 英文描述： | Ten Distributed-Output Clock Driver |
| 中文描述： | 十分布式輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 151K |
| 代理商： | W132-10BX |
W134M/W134S
Document #: 38-07426 Rev. *A
Page 9 of 13
Notes:
2.
3.
4.
5.
6.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Refclk jitter measured at V
(nom)/2.
If input modulation is used: input modulation is allowed but not required.
Capacitance measured at Freq=1 MHz, DC bias = 0.9V and V
< 100 mV.
The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Table 13. Operating Conditions
[2]
Parameter
V
DD
Supply Voltage
T
A
Ambient Operating Temperature
t
CYCLE,IN
Refclk Input Cycle Time
t
J,IN
DC
IN
Input Duty Cycle over 10,000 Cycles
FM
IN
Input Frequency of Modulation
PM
IN[4]
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
t
CYCLE,PD
Phase Detector Input Cycle Time at PclkM & SynclkN
t
ERR,INIT
Initial Phase error at Phase Detector Inputs
DC
IN,PD
Phase Detector Input Duty Cycle over 10,000 Cycles
t
I,SR
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,
SynclkN, and Refclk
C
IN,PD
C
IN,PD
C
IN,CMOS
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and
Refclk)
[5]
V
IL
Input (CMOS) Signal Low Voltage
V
IH
Input (CMOS) Signal High Voltage
V
IL,R
Refclk input Low Voltage
V
IH,R
Refclk input High Voltage
V
IL,PD
Input Signal Low Voltage for PD Inputs and StopB
V
IH,PD
Input Signal High Voltage for PD Inputs and StopB
V
DDIR
Input Supply Reference for Refclk
V
DDIPD
Input Supply Reference for PD Inputs
Description
Min.
3.135
0
10
-
40
30
--
--
30
–
0.5
25
1
Max.
3.465
70
40
250
60
33
0.6
0.5
[6]
100
0.5
75
4
Unit
V
°
C
ns
ps
%t
CYCLE
kHz
%
%
ns
t
CYCLE,PD
t
CYCLE,PD
V/ns
Input Cycle-to-Cycle Jitter
[3]
Input Capacitance at PclkM, SynclkN, and Refclk
[5]
Input Capacitance matching at PclkM and SynclkN
[5]
-
-
-
7
pF
pF
pF
0.5
10
-
0.3
-
0.3
-
0.3
-
3.465
2.625
VDD
VDD
V
DDIR
V
DDIR
V
DDIPD
V
DDIPD
V
V
0.7
-
0.7
-
0.7
1.235
1.235
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相關(guān)代理商/技術(shù)參數(shù) |
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| W132-10BXT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 25MHz to 140MHz 24-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:CLK DRIVER - Tape and Reel |
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| W132MPCX-2 | 制造商:Struthers-Dunn 功能描述: |
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