參數(shù)資料
型號: W.A.R.P.2.0
英文描述: 8-BIT FUZZY CO-PROCESSOR
中文描述: 8位模糊協(xié)處理器
文件頁數(shù): 9/28頁
文件大?。?/td> 275K
代理商: W.A.R.P.2.0
Output Port.
This block provides the output data
supported by handshaking signals. Ouput data
resolution is 8 bit.
An output ready on the bus O0-O7 is indicated by
a DS pulse and by its identificationnumber (OC0-
OC1). WAIT active temporarily stops the elabora-
tionphaseallowingthesynchronizationwithslower
devices.
Programmable A/D output pulse.
This block al-
lows to programthe widthof the pulseprovided on
O11 (only in On-Line mode)that can beused as a
Start Conversion foran externalA/D. The width of
this pulse can be configured by means of the
related register (see register bench description)
following the table 4.
Startconversion
Pulse Register
Low, Low, Low
Low, Low, High
Low,High, Low
Low, High, High
High, Low, Low
High, Low, High
High, High, Low
High, High, High
Pulse Width
(T
CLK
= MCLK Period)
128xT
CLK
256xT
CLK
2040xT
CLK
4080xT
CLK
8160xT
CLK
16320xT
CLK
32000xT
CLK
65520xT
CLK
Table 4. Start ConversionPulse (O11) Width
Setting.
9/28
W.A.R.P.2.0
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