- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361756 > W.A.R.P.1.1 WEIGHT ASSOCIATIVE RULE PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | W.A.R.P.1.1 |
| 英文描述： | WEIGHT ASSOCIATIVE RULE PROCESSOR |
| 中文描述： | 重量的聯(lián)想規(guī)則處理器 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大小： | 275K |
| 代理商： | W.A.R.P.1.1 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
PINDESCRIPTION
Signals READY, RD, WAIT, DS, BUSY, LASTIN
and O11 ( external A/D Start Conversion) have
programmable polarity, see table 6 for default
values.
V
DD
, V
SS
.
Power is supplied to W.A.R.P. using
these pins. V
DD
isthe power connectionand V
SS
is
the ground connection;multi-connections are nec-
essary.
MCLK.
Master Clock (Input)
:
This is the input
master clock whose frequency can reach up to
40MHz(MAX).
During the Off-Line phase with AUTO
High
, the
MCLKis internally divided to utilize boot memories
workingwith aslowerfrequency.Theaccessspeed
is presettableby means of SIS0-SIS2pins.
PRESET.
Preset (Input, active Low)
:
This is the
restart pin of W.A.R.P.. It is possible to restart the
work during the computation (On-Line phase) or
before the writing of internal memories (Off-Line
phase). In both cases it must be put
Low
at least
for a clock period. After PRESET
Low
the proces-
sor remains in the reset status 3 MCLKpulses.
AUTO.
Auto-Boot:(Input,active High)
:
During the
Off-Line phase AUTO
High
enablesthe automatic
bootof W.A.R.P.2.0whereas AUTO
Low
validates
the manual downloading.The manualboot has to
be performed using the handshaking signals
RD/READY.
During the On-Line phase AUTO
High
disables
the generationof the Start A/D conversion (O11)
signal.
SIS0-SIS2.
Speed & Input Selection(Inputs): Dur-
ingtheOff-LinephasewithAUTO
High
(Auto-Boot)
SISbusallows tochoosethespeedofdownloading
fromthe externalmemorywhich contains thestart-
up configurationof W.A.R.P.2.0.In thatcase(Auto-
Boot)MCLK isinternallydividedtoprovide aslower
sinchronization signal which is automaticallyused
asRDfor thereadingof theexternalmemory. Table
2 shows how to preset the frequency of this syn-
chronizationsignal.
During the On-Line phase in Slave mode (see
RegisterBench description, Tab.5)SIS bus allows
to provide W.A.R.P.2.0with inputs in any order by
specifying their identification number. The input
and its identification number (SIS0-SIS2) will be
acquired at the next active RD so they must be
already stable when RD is given.
SIS0
SIS1
SIS2
Internal Synchronization
Signal Frequency
MCLK/32
MCLK/16
Low
High
Low
Low
Low
Low
Table 2. DownloadingSpeed
I0-I7.
Input bus (Input)
:
During the Off-Line phase
these 8datainputpins acceptaddresses and data
from the external boot memory containing
W.A.R.P.2.0 configuration. This start-up memory
(which can be a ZERO-POWER, the host proces-
sor memory, an EPROM, aFlash,the PC Memory,
etc.) contains the fuzzy project built by means of
FUZZYSTUDIO
2.0.
In On-Linemodethisbus carriestheinputvariables
according to the prefixedorder.
OFL.
Offline(Input, active High)
:
When this pin is
High
, thechipisenabledto loaddataintheinternal
RAMs (Off-Line phase). It must be
Low
when the
fuzzy controller is waiting for input values and
during the processingphase (On-Linephase).
When OFL changes its status the processor re-
mains presettedfor 3 clockpulses.
LASTIN.
Last Input (Input, default active High):
During the On-Line phase in slave mode (see
RegisterBench description, table 5) LASTIN
High
indicates no other inputs have to be provided so
W.A.R.P.2.0can start the processingphase.
W.A.R.P.2.0inputs are those in the input interface
so if some variables do not need to be acquired
again (because they change slower than others)
they remain stored and no extra time isrequired to
acquire them again.
OE.
Output Enable (Input, active Low): OE
Low
enables O0-011output bus or (if
High
) put it in
3-STATE.
WAIT.
Wait (Input, default active High): This pin
High
stops the output processing. When WAIT is
enabled W.A.R.P.2.0 finishes to computethe cur-
rent output variable but it does not give it on the
output bus until WAIT becomes
Low
. This signal
allows to synchronize W.A.R.P.2.0with slower de-
vices.
RD.
Read
(Input, default active High): Both in
Off-Line and in On-Line mode RD indicates data
are ready to be acquired from the input bus I0-I7.
READY.
Ready(Output,defaultactive High):Both
in Off-Lineand in On-Linemode RD indicates data
have been acquired from the input bus I0-I7 and
are now storedin W.A.R.P.2.0 internalregisters.
ENDOFL.
End of Off-Line phase (Output, active
High): This pin indicates the end of the download-
ing phase (Off-Line) so the content of the boot
memory is already stored in W.A.R.P.2.0 internal
memories.AfterENDOFL isactivetheuser canput
OFL
Low
so the On-Line phase can start.
BUSY.
Busy Signal (Output, defaultactive High):
When the elaborationphase is running this pin is
active. When W.A.R.P.2.0finishes to compute the
last output variable, it puts BUSY
Low
and waits
for new inputs.
4/28
W.A.R.P.2.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W.A.R.P.2.0 | 8-BIT FUZZY CO-PROCESSOR |
| W024400 | VACUUM PIC-UP PEN ESD |
| W0512HD2 | DC to DC Converter |
| W0515GD2 | DC to DC Converter |
| W0515HD2 | DC to DC Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WARP20 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT FUZZY CO-PROCESSOR |
| WARRANTY REPAIR | 制造商:PREMIER FARNELL 功能描述:WARRANTY REPAIR |
| WARREXT2YR-140 | 制造商:Kontron 功能描述:EXTENDED WARRANTY - Bulk |
| WARR-PVI266-15YR | 制造商:Solectria 功能描述: |
| WARR-PVI95-15YR | 制造商:Solectria 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。