參數(shù)資料
型號(hào): VV6501
廠商: 意法半導(dǎo)體
英文描述: DUAL-MODE DIGITAL CAMERA CO-PROCESSOR
中文描述: 雙模式數(shù)字相機(jī)協(xié)處理器
文件頁(yè)數(shù): 38/44頁(yè)
文件大?。?/td> 351K
代理商: VV6501
STV0681 pin description
STV0681
38/44
ADCS 7283313C
28
AD13
Output
SDRAM address A13, BA1 for 64M SDRAM, unused
on 16M
2mA
(SL)
25
CS
Output, active low
Chip select: enables (registered LOW) and disables
(registered HIGH) the SDRAM command decoder.
2mA
(SL)
23
RAS
Output, active low
SDRAM row address strobe command
2mA
(SL)
21
CAS
Output, active low
SDRAM column address strobe command
2mA
(SL)
19
WE
Output, active low
SDRAM write enable command
2mA
(SL)
18
DQML
Output
Data input/output mask for dram_DQ[7:0]
2mA
(SL)
100
DQ0
Input/Output
SDRAM Data Bus
2mA
(SL)
2
DQ1
Input/Output
SDRAM Data Bus
2mA
(SL)
4
DQ2
Input/Output
SDRAM Data Bus
2mA
(SL)
6
DQ3
Input/Output
SDRAM Data Bus
2mA
(SL)
8
DQ4
Input/Output
SDRAM Data Bus
2mA
(SL)
10
DQ5
Input/Output
SDRAM Data Bus
2mA
(SL)
14
DQ6
Input/Output
SDRAM Data Bus
2mA
(SL)
16
DQ7
Input/Output
SDRAM Data Bus
2mA
(SL)
17
DQ8
Input/Output
SDRAM Data bus
2mA
(SL)
15
DQ9
Input/Output
SDRAM Data bus
2mA
(SL)
13
DQ10
Input/Output
SDRAM Data bus
2mA
(SL)
9
DQ11
Input/Output
SDRAM Data Bus
2mA
(SL)
7
DQ12
Input/Output
SDRAM Data Bus
2mA
(SL)
5
DQ13
Input/Output
SDRAM Data Bus
2mA
(SL)
3
DQ14
Input/Output
SDRAM Data Bus
2mA
(SL)
1
DQ15
Input/Output
SDRAM Data Bus
2mA
(SL)
Table 15: STV0681 pin listing
Pin no.
Signal
Type
Description
drive
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