參數(shù)資料
型號: VV6444
廠商: 意法半導體
英文描述: Low Cost Digital Camera (LCDC) Chipset
中文描述: 低成本數(shù)碼相機(LCDC)芯片組
文件頁數(shù): 56/60頁
文件大?。?/td> 352K
代理商: VV6444
PRELIMINARY
Digital Camera Chipset; Customer Datasheet, Rev 3.0, March 2000
STV0680A + VV6444/6410/6500
CDSTV0680F-C
Commercial in confidence
56
T
STV0680F_500_pckg.fm
CLKIN
40
BI
LVDS negative Clock input
LST/D[5]
37
ODT
Tri-stateable Line start output
May be configured as tri-stateable output data bit 5 D[5].
FST/D[6]
38
ODT
Tri-stateable Frame start signal.
May be configured as tri-stateable output data bit 6 D[6].
D[7]
41
ODT
Tri-stateable Data wire (ms data bit).
May be configured as tri-stateable output data bit 6 D[6].
OEB
20
ID
Digital output (tri-state) enable.
DIGITAL CONTROL SIGNALS
RESETB
31
ID
System Reset. Active Low.
May be configured as System Sync. Active Low.
SUSPEND
31
ID
USB Suspend Mode Control signal. Active High
If this feature is not required then the support circuit must pull the pin to
ground. The combination of an active high signal and pull up pad was
chosen to limit current drawn by the device while in suspend mode.
SERIAL INTERFACE
SCL
18
BI
Serial bus clock (input only).
SDA
17
BI
Serial bus data (bidirectional, open drain).
SYSTEM CLOCKS
CLKI/CLKIP
39
ID
Schmitt Buffered Clock input or LVDS positive Clock input
Not connected
NC
10, 14, 19, 22-
28, 48
Not connected
Key
A
Analog Input
D
Digital Input
OA
Analog Output
ID
Digital input with internal pull-up
BI
Bidirectional
ID
Digital input with internal pull-down
BI
Bidirectional with internal pull-up
OD
Digital Output
BI
Bidirectional with internal pull-down
ODT
Tri-stateable Digital Output
Name
Pin Number
Type
Description
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