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參數(shù)資料
| 型號： | VV6410C036 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC36 |
| 封裝： | LCC-36 |
| 文件頁數(shù)： | 51/63頁 |
| 文件大?。?/td> | 563K |
| 代理商： | VV6410C036 |
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Version 3.4
55/63
STV0680B+ VV6410/6411/6500
VV6500 pinout information and package dimensions
Digital video interface
D[4]
D[3]
D[2]
D[1]
D[0]
36
35
34
33
32
ODT
Tri-stateable 5-wire output data bus.
- D[4] is the most significant bit.
- D[4:0] have programmable drive strengths 2, 4 and 6 mA
QCK
42
ODT
Tri-stateable data qualification clock.
CLKIN
40
BI
↑
LVDS negative Clock input
LST/D[5]
37
ODT
Tri-stateable Line start output
May be configured as tri-stateable output data bit 5 D[5].
FST/D[6]
38
ODT
Tri-stateable Frame start signal.
May be configured as tri-stateable output data bit 6 D[6].
D[7]
41
ODT
Tri-stateable Data wire (ms data bit).
May be configured as tri-stateable output data bit 6 D[6].
OEB
20
ID
↓
Digital output (tri-state) enable.
Digital control signals
RESETB
31
ID
↑
System Reset. Active Low.
May be configured as System Sync. Active Low.
SUSPEND
31
ID
↑
USB Suspend Mode Control signal. Active High
If this feature is not required then the support circuit must pull the pin to
ground. The combination of an active high signal and pull up pad was
chosen to limit current drawn by the device while in suspend mode.
Serial interface
SCL
18
BI
↑
Serial bus clock (input only).
SDA
17
BI
↑
Serial bus data (bidirectional, open drain).
System clocks
CLKI/CLKIP
39
ID
↓
Schmitt Buffered Clock input or LVDS positive Clock input
Not connected
NC
2, 7, 8, 10,13,
14, 19, 22-28,
48
Not connected
Key
A
Analogue Input
D
Digital Input
OA
Analogue Output
ID
↑
Digital input with internal pull-up
BI
Bidirectional
ID
↓
Digital input with internal pull-down
BI
↑
Bidirectional with internal pull-up
OD
Digital Output
BI
↓
Bidirectional with internal pull-down
ODT
Tri-stateable Digital Output
Name
Pin Number
Type
Description
Table 21 : VV6500 pin description
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