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參數(shù)資料
| 型號： | VT98501S1X |
| 廠商： | Vaishali Semiconductor |
| 英文描述： | 3.3V Low Phase Noise Clock Multiplier |
| 中文描述： | 3.3V的低相位噪聲時鐘乘法器 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 77K |
| 代理商： | VT98501S1X |
VT98501
Table 2. Examples of Common Output Frequencies.
Output
20
24
Input
10
12
Selection (S1,S0)
M,M
M,M
Output
50
60
Input
16.66
10
Selection (S1,S0)
1,M
1,0
Output
83.33
90
Input
16.66
15
Selection (S1,S0)
0,1
1,0
Table 3. Pin Description
No.
Name
Type
Description
1
X1/ICLK
I
Xtal connection or clock input.
2
VDD
P
Connect to +3.3V
3
GND
P
Connect to ground.
4
S1
TI
Select 1 for output clock. Connect to ground or VDD or float
5
CLK
O
Clock output per table 2.
6
S0
TI
Select 0 for output clock. Connect to ground or VDD or float.
7
OE
I
Output Enable. Tri- states CLK output when low.
8
X2
O
Xtal connection. Leave unconnected for clock input.
Legend:
I = Input
TI = Tri-level Input
O = Output
P = Power supply connection
Advance Information
2001-03-05
Vaishali Semiconductor 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Page 2
MDST-0009-00
30
10
1,M
32
16
M,M
33.33
16.66
M,M
37.5
12
M,1
40
10
0,0
48
12
0,0
62.5
20
M,1
64
16
0,0
66.66
16.66
0,0
72
12
1,0
75
12
M,0
80
10
1,1
100
20
0,1
106.25
20
0,M
120
15
1,1
125
20
M,0
155.52
19.44
1,1
Table 1. Clock Output Table
S1
S0
CLK
0
0
4 x input
0
M
5.3125 x input
0
1
5 x input
M
0
6.25 x input
M
M
2 x input
M
1
3.125 x input
1
0
6 x input
1
M
3 x input
1
1
8 x input
0 = Connect to ground.
1 = Connect dir ectl y to VDD
M = Leave unconnected (f l oating)
Minimum Input
See table 7
20 MHz
See table 7
4 MHz
See table 7
8 MHz
See table 7
See table 7
See table 7
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