參數(shù)資料
型號: VT8225
廠商: Electronic Theatre Controls, Inc.
英文描述: Clock Generator
中文描述: 時(shí)鐘發(fā)生器
文件頁數(shù): 2/4頁
文件大?。?/td> 20K
代理商: VT8225
VIA Technologies, Inc.
VT8225
-2-
VT8225 Signal Description
Symbol Pin No.
X1
Type
I
Functions
X2
2
3
I/O
These pins form an on-chip reference oscillator when connected to
terminals of an external parallel resonant crystal (norminally
14.318Mhz). X1 may also serve as input for an externally
generated reference signal.
Frequency select inputs. These inputs control the MCLK frequency
selection. All these inputs have internal pull-ups. Table 1 below
shows the output frequency selection conditions.
S0
S1
S2
S3
MCLK
4
5
10
9
8
I
I
I
I
O
Master clock output. Programmable output frequencies can
be selected using So-S3.
Chip reset, negative true.
Tri-state input pin. When high, all outputs are tri-stated. When low
outputs are enabled. This pin has an internal pull-down.
14.31818 Mhz output. Buffered output of on-chip reference
oscillaor or externally provided reference.
This is the phase detector output for the clock generator. It is
single-ended, tri-state output for use as loop error signal. A 0.1uF
capacitor to ground should be connected from this pin to form the
loop filter.
Digital Negative power supply.
Analog Negative power supply.
Positive power supply.
RESET#
11
O
TS
OSC
1
13
I
O
PD
6
O
VSS
AVSS
VDD
7
Ground
Ground
Power
12
14
MCLK FREQUENCY SELECTION
INPUTS
S1
S0
S3=1 (Bank 1)
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
MCLK OUTPUT
S2
0
0
0
0
1
1
1
1
S3=0 (Bank 0)
16 Mhz
40 Mhz
50 Mhz
80 Mhz
66.6 Mhz
100 Mhz
8 Mhz
4 Mhz
8 Mhz
20 Mhz
25 Mhz
40 Mhz
33.3 Mhz
50 Mhz
4 Mhz
2 Mhz
Table 1 clock frequency selection
Note : The smooth transition of frequency change is only allowed within the same selection bank.
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