參數(shù)資料
型號(hào)： VT73LVP10S1X
廠商： Vaishali Semiconductor
英文描述： TTL to Differential LVPECL Translator
中文描述： TTL到差分LVPECL翻譯
文件頁(yè)數(shù)： 2/3頁(yè)
文件大小： 69K
代理商： VT73LVP10S1X
VT73LVP10
Preliminary
2002-01-15
Page
2
MDST-0014-06
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Table 1. Pin Description
Name
/EN
Description
Type
I
Pin #
4*
CMOS/TTL Active LOW enable input, with pull-down resistor
Q
PECL data output
O
2
QN
PECL complementary data output
O
3
V
DD
Connect to 3.3V
P
8
D
CMOS/TTL data input
I
7
GND
Connect to ground
P
5
Legend: I = Input
O = Output
P = Power supply connection
* = Internal 100k
pull-down resistor
Table 2. Absolute Maximum Ratings
Symbol
V
DD
Parameter
Conditions
Referenced to GND
Min
Typ
Max
6
Units
V
Supply voltage
V
IN
Input voltage
Referenced to GND
-0.5
6
V
I
OUT
Output current in LOW state
50
mA
T
STG
Storage temperature
-65
150
o
C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Table 3. Operating Conditions
Symbol
V
DD
Parameter
Power Supply Voltage
Conditions
Min
3.0
Typ
Max
3.6
Units
V
T
A
Ambient Temperature
-40
85
o
C
V
IH
Input HIGH Voltage
D, /EN inputs
2.0
V
V
IL
Input LOW Voltage
D, /EN inputs
0.8
V
t
Rin
Input slew rate
10% to 90% (L
→
H)
1
V/ns
t
Fin
Input slew rate
90% to 10% (H
→
L)
1
V/ns
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