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參數(shù)資料
| 型號： | VSP2262K |
| 英文描述： | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 224K |
| 代理商： | VSP2262K |
VSP2262
SBMS011
8
FIGURE 2. The Characteristics of PGA Gain.
TABLE I. Programmable OB Clamp Level.
(Negative Reference, pin 39), and CM (Common-Mode
Voltage, pin 37) should be bypassed to ground with a 0.1
μ
F
ceramic capacitor and should not be used elsewhere in the
system, as they affect the stability of these reference levels,
which causes ADC performance degradation. Note that
these are analog output pins and, therefore, do not apply
external voltage.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Figure 2 shows the characteristics of the PGA gain. The PGA
provides a gain range of –6dB to +42dB, which is linear in dB.
The gain is controlled by a digital code with
10-bit resolution, and can be set through the serial interface
(refer to the “Serial Interface” section for more detail). The
default value of the gain control code is 128 (PGA Gain =
0dB)
.
However, immediately after power ON, this value is
Unknown. For this reason, the appropriate value must be set
by using the serial interface, or reset to the default value by
strobing the RESET pin.
OPTICAL BLACK (OB) LEVEL CLAMP LOOP
To extract the video information correctly, the CCD signal
must be referenced to a well-established OB level. The
VSP2262 has an auto-calibration loop to establish the OB
level using the optical black pixels output from the CCD
imager. The input signal level of the OB pixels is identified
as the real “OB level”, and the loop should be closed while
CLPOB is active.
During the effective pixel interval, the reference level of the
CCD output signal is clamped to the OB level by the OB
level clamp loop. To determine the loop time constant, an
off-chip capacitor is required, and should be connected to
COB (pin 28). Time constant T is given in the following
equation:
T = C/(16384 I
MIN
)
Where C is the capacitor value connected to COB, I
MIN
is the
minimum current (0.15
μ
A) of the control Digital-to-Analog
Converter (DAC) in the OB level clamp loop, and 0.15
μ
A is
equivalent to 1LSB of the DAC output current. When C is
0.1
μ
F, time constant T is 40.7
μ
s.
Additionally, the slew rate SR is given the following equa-
tion:
SR = I
MAX
/C
Where C is the capacitor value connected to COB, I
MAX
is
the maximum current (153
μ
A) of the control DAC in the OB
level clamp loop, and 153
μ
A is equivalent to 1023LSB of
the DAC output current.
Generally, OB level clamping at high speed causes “Clamp
Noise” (or “White Streak Noise”), however, the noise will
decrease by increasing C. On the other hand, an increased C
requires a much longer time to restore from Stand-by mode,
or right after power ON. Therefore, we consider 0.1
μ
F to
0.22
μ
F a reasonable value for C. However, it depends on the
application environment; we recommend making careful
adjustments using trial-and-error.
The “OB clamp level” (the pedestal level) is programmable
through the serial interface (refer to the “Serial Interface”
section for more detail). Table I shows the relationship
between input code and the OB clamp level.
The active polarity of CLPOB (Active HIGH or Active
LOW) can be selected through the serial interface (refer to
the “Serial Interface” section for more detail). The default
value of CLPOB is “Active LOW”. However, immediately
after power ON, this value is Unknown. For this reason, the
appropriate value must be set by using the serial interface, or
reset to the default value by strobing the RESET pin. The
descriptions and the timing diagrams in this data sheet are all
based on the polarity of Active LOW (default value).
PREBLANKING AND DATA LATENCY
The VSP2262 has an input blanking, or preblanking, func-
tion. When PBLK goes LOW, all digital outputs will go to
ZERO at the 11th rising edge of ADCCK. In this mode, the
digital output data comes out on the rising edge of ADCCK
with a delay of 11 clock cycles (data latency is 11). This is
INPUT CODE
OB CLAMP LEVEL, LSBs OF 12 BITS
0000
0001
0010
0011
0100
0101
0110
0111
2LSB
18LSB
34LSB
50LSB
66LSB
82LSB
98LSB
114LSB
130LSB
146LSB
162LSB
178LSB
194LSB
210LSB
226LSB
1000 (Default)
1001
1010
1011
1100
1101
1110
1111
242LSB
Input Code for Gain Control (0 to 1023)
G
50
40
30
20
10
0
–
10
0
1
2
3
4
5
6
7
8
9
1
1
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| VSP2262Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2262Y/2K | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2262Y/2KG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2262YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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