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參數(shù)資料
| 型號： | VSC8169 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator |
| 中文描述： | MUX/DEMUX, PQFP128 |
| 封裝： | 14 X 20 MM, HEAT SINK, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 191K |
| 代理商： | VSC8169 |
VITESSE
Preliminary Data Sheet
VSC8169
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
G52230-0, Rev 3.6
01/02/01
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
16:1 Multiplexer Up to 2.7Gb/s
Targeted for SONET OC-48 / SDH STM-16 (FEC)
Applications
Differential LVPECL Low-Speed Interface
General Description
The VSC8169 is a 16:1 multiplexer with integrated clock generator for use in SONET/SDH systems oper-
ating at a standard 2.48832Gb/s data rate or a forward error correction (FEC) data rate up to 2.7Gb/s. The inter-
nal clock generator uses a Phase-Locked Loop (PLL) to multiply either a 77.76MHz (up to 84.38MHz-FEC) or
a 155.52MHz (up to 168.75MHz -FEC) reference clock in order to provide the 2.48832GHz (up to 2.7GHz -
FEC) clock for internal logic and output retiming. For use with the VSC9210 FEC Encoder/Decoder chipset
running at 2.654208Gb/s, a reference clock of 82.944MHz (serial rate divided by 32) should be used. The 16-bit
parallel interface incorporates an on-board FIFO eliminating loop timing design issues by providing a flexible
parallel timing architecture. The device operates using a 3.3V power supply, and is packaged in a thermally-
enhanced plastic package. The thermal performance of the 128-pin PQFP allows the use of the VSC8169 with-
out a heat sink under most thermal conditions.
VSC8169 Block Diagram
On-Chip PLL-Based Clock Generator
128-Pin 14x20mm PQFP Package
Single +3.3V Supply
D0-
D0+
D15-
D15+
CLK16O-
I
Output
Retime
2.6GHz
PLL
REFCLK-
REFCLK+
CLK16O+
DO-
DO+
1
CLK16I-
CLK16I+
Write
Pointer
Read
Pointer
FIFO
Control
Reset
Divide by 16
FIFO_WAR
CLKO+
CLKO-
F_FREQSEL
REFCLKO-
REFCLKO+
Divide
by 2
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