參數(shù)資料
型號(hào): VSC8062FC
廠商: Vitesse Semiconductor Corporation.
英文描述: 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset
中文描述: 容量高達(dá)2.5GB / s的16位復(fù)用器/解復(fù)用器芯片組
文件頁數(shù): 3/20頁
文件大?。?/td> 684K
代理商: VSC8062FC
VITESSE
G52069-0, Rev 4.3
05/11/01
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Data Sheet
VSC8061/VSC8062
Multiplexer/Demultiplexer Chipset
2.5Gb/s 16-Bit
VSC8061 Multiplexer AC Characteristics
(Over recommended operating range)
Figure 3: VSC8061 Multiplexer Waveforms
Table 1: VSC8061 AC Characteristics
NOTE: (1) Devices are guaranteed to operate to a maximum frequency of 2.5GHz.
Parameter
Description
Min
Typ
Max
Units
Conditions
t
CLK
t
D
Clock period
(1)
400
ps
CLK16, DCLK period (t
CLK
x 16)
Parallel data set-up time with respect to CLK16
falling edge
6.4
15.6
ns
t
DSU
2.0
ns
t
DH
Data hold time with respect to CLK16 falling
edge
0.5
ns
t
DC
t
R
, t
F
t
R
, t
F
t
R
, t
F
t
R
, t
F
CLK16 duty cycle
40
60
%
DCLK (DCLKN) rise and fall times
1.5
ns
10% to 90%
D[0:15] rise and fall times
2.0
ns
10% to 90%
CLK16 (CLK16N) rise and fall times
0.5
1.0
ns
10% to 90%
DO (DON) rise and fall times
150
165
ps
20% to 80%
VALID DATA (1)
VALID DATA (2)
D0
D1 D2
D3 D4
D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15
High-speed differential clock input
Parallel data clock output
Parallel data inputs
Parallel data clock input
High-speed differential serial data output
CLK (CLKN)
CLK16 (CLK16N)
D[0:15]
DCLK (DCLKN)
DO (DON)
Serialized Data
t
D
t
D
t
D
t
DH
t
DSU
t
CLK
NOTE:
=
Don’t care
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相關(guān)代理商/技術(shù)參數(shù)
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VSC8062FI 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset
VSC8062QH 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset
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VSC8071BA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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