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參數(shù)資料
| 型號(hào)： | VSC7961YD |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.125Gb/s PECL Limiting Amplifier with LOS Detect |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大小： | 95K |
| 代理商： | VSC7961YD |
VITESSE
Advance Product Information
VSC7961
3.125Gb/s PECL Limiting Amplifier with LOS Detect
Page 2
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Electrical Characteristics
Table 1: DC Specifications
NOTE: (1) See Figure 4 for supply current measurement setup.
Table 2: DC Specifications
NOTES: (1) Deterministic jitter measured peak-to-peak with K28.5 pattern. (2) Random jitter measured with minimum input.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
CC
Power Supply Voltage
3.135
5.5
V
I
CC
Power Supply Current
(1)
59
62
31
35
58
62
20
23
mA
mA
mA
m
Α
mA
mA
mA
mA
μA
dB
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
I
EE
Power Supply Current
(1)
I
CCSQ
Power Supply Current when
Squelched
(1)
I
EESQ
Power Supply Current when
Squelched
(1)
I
SQ
PSSR
Squelch Input Current
Power Supply Rejection Ratio
0
400
20
f < 2MHz
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Data Rate
Input Voltage Range
Deterministic Jitter
Random Jitter
Rise and Fall Times
Input Referred Noise
Differential Input Resistance
3.125
10
Gb/s
mV
ps
ps
ps
μV
MHz
kHz
mV
mV
mV
mV
mV
V
IN
J
D
J
R
t
R,
t
F
V
N
R
DIFF
1200
25
8
100
230
Peak-to-peak
See Note 1
See Note 2, RMS
20% to 80%
RMS, IN+ to IN-
IN+ to IN-
C
Z
open
C
Z
= 0.1μF
Output AC-coupled
55
100
2
2
f
L
Low Frequency Cutoff
V
SQ
Output Signal When Squelched
20
-850
-850
-1620
-1620
V
OH
PECL Output High Voltage
-1025
Squelched
V
OL
PECL Output Low Voltage
-1810
Squelched
Single-ended
Z
O
Output Resistance
100
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