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參數(shù)資料
| 型號： | VSC7146 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | BOX 4.94X2.75X1.275 W/CLP ALMOND |
| 中文描述： | 2.5GB的/秒，20位收發(fā)器 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 251K |
| 代理商： | VSC7146 |
VITESSE
SEMICONDUCTOR CORPORATION
7
41 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 7
8/28/00
VITESSE
Advance Product Information
VSC7146
2.5Gb/s, 20-Bit Transceiver
G52162-0, Rev. 2.7
Figure 5: Receive Timing Waveforms
Table 4: Receive AC Characteristics
Paramete
rs
Description
Min.
Max.
Units
Conditions
T
1
Data or COM_DET valid prior to
RBCN rise
1.0
2.0
—
ns
Measured between the 1.4V point of
RBCN and a valid level of R[0:19] or
COM_DET. All outputs driving 10pF load.
The spec on top relects RXMODE=1 and
the bottom one reflects RXMODE=0.
T
2
Data or COM_DET valid after
RBCN rise
5.0
10.0
—
ns
T
3
Time difference between RBC and
RBCN edges
—
1
ns
T
R1
, T
F1
RBC/RBCN rise and fall time
0.6
2.0
ns
Between V
IL
(max) and V
IH
(min), into
10pF load.
Between V
IL
(max) and V
IH
(min), into
10pF load.
T
R2
, T
F2
R[0:19], COM_DET rise and fall
time
0.7
2.4
ns
R
LAT
Latency from RX to R[0:19]
36bc+
2ns
7.9
15.8
40%
56bc+
2ns
8.1
16.2
60%
Bit
Clocks
When locked to valid data.
T
RBC
RBC period
ns
The spec on top relects RXMODE=1 and
the bottom one reflects RXMODE=0.
DC
RBC duty cycle
Data acquisition lock time @
2.5Gb/s
period
Bit
Clocks
T
LOCK
—
1250
Tested on a sample basis. 95% probability
of lock.
RBCN
R[0:19] and
COM_DET
T
2
Data Valid
Data Valid
T
1
T
3
Data Valid
RBC
T
3
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