參數(shù)資料
型號(hào): VSC7127
廠商: Vitesse Semiconductor Corporation.
英文描述: Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
中文描述: 家庭的中繼/重定時(shí)器和端口旁路電路的光纖通道
文件頁(yè)數(shù): 6/12頁(yè)
文件大小: 174K
代理商: VSC7127
Data Sheet
VSC7127/VSC7129
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
VITESSE
Page 6
G52298-0, Rev 4.3
05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 4: REFCLK Timing Waveforms *
Table 2: Reference Clock Requirements
DC Characteristics
(Over recommended operating conditions)
NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.
Parameters
Description
Min
Typ
Max
Units
Conditions
FR
Frequency Range
105
107
MHz
FO
Frequency Offset
-200
200
ppm
Maximum frequency offset
between transmit and receive
reference clocks on one link
Measured at 1.5V
Between V
IL(MAX)
and V
IH(MIN)
DC
T
R
, T
F
Duty Cycle
Rise and Fall Time
35
65
2.0
%
ns
Parameters
Description
Min
Typ
Max
Units
Conditions
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
TX output differential peak-to-
peak voltage swing
TX output differential peak-to-
peak voltage swing
Receiver differential peak-to-peak
input Sensitivity RX
Supply voltage
2.4
V
V
V
V
μA
μA
I
OH
= -1.0mA
I
OL
= +1.0mA
0.5
5.5
0.8
500
-500
2.0
0
50
V
IN
=2.4V
V
IN
=0.5V
V
OUT75(1)
1200
2200
mVp-p
75
to V
DD
2.0 V
V
OUT50(1)
1000
2200
mVp-p
50
to V
DD
2.0 V
V
IN(1)
400
2600
mVp-p
Internally biased to V
DD
/2
V
DD
3.14
3.47
V
3.3V±5%
Outputs open, V
DD
= V
DD
max.
±2%
Outputs open, V
DD
= V
DD
max
V
DDA
= V
DD
max
P
D
Power dissipation
707
902
mW
I
DD
I
DDA
Current (all supplies)
Current (V
DDA
)
215
50
260
70
mA
mA
REFCLK
V
IL(MAX)
V
IH(MIN)
NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state.
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