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參數(shù)資料
| 型號： | VSC6511 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s |
| 中文描述： | 的SMPTE - 292M的串行器，解串器，并串器/時鐘恢復器/在1.485Gb ? |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 379K |
| 代理商： | VSC6511 |
VITESSE
Advance Product Information
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
VSC6511
Page 10
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
4/10/00
G52311-0, Rev 2.0
D
Features: Deserializer Mode
1.
Compliant with SMPTE-292M @ 1.485Gb/s
2.
Clock and Data Recovery
3.
1:20 Deserializer
4.
Descrambler and NRZI Decoder with ENABLE
5.
Data Framer aligns data to SAV/EAV
6.
On-chip Clock Multiplier Unit
7.
CRC Checker
8.
LINE, FRAME, HANC Indication
9.
3.3V, 800 mW -- typical power
10. 20 Bit TTL Interface @ 74.25 MHz
General Description
The VSC6511 can be configured as a 20-bit HDTV Deserializer using the MODE[1:0] pins. Serial data
from SDI/SDI is sent to the Clock Recovery Unit (CRU) for clock extraction and data resynchronization. Then
the serial data is descrambled/NRZI decoded, deserialized and output on D[19:0] synchronously by a divided-
by-twenty recovered clock, RCLK. A CRC Checker monitors the output data and indicates any CRC errors on
the CRC pin. Descrambling is enabled by SCREN being HIGH. Data framing aligns the SAV/EAV patterns in
the data with the data bus and RCLK and generates a once-per-line and once-per-frame synchronization output.
A signal detect function on SDI/SDI monitors the quality of the serial input.
Figure 5: Deserializer Mode
1001
LINE
FRAME
HANC
SDI
SDI
Clock
Recovery
Unit
REFCLK
74.25 MHz
Clock
Multiply
x20
1.485 GHz
RCLK
SCREN
1.485 GHz
D[19:0]
SIGDET
/20
CRC Check
Deserializer
D Q
Framer
CRCERR
NRZI Decoder
Descrambler
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