參數(shù)資料
型號(hào): VS8062FC
廠商: VITESSE SEMICONDUCTOR CORP
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, CQFP52
封裝: HEAT SINK, CERAMIC, LDCC-52
文件頁(yè)數(shù): 15/20頁(yè)
文件大?。?/td> 409K
代理商: VS8062FC
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC8061/VSC8062
2.5 Gb/s 16-Bit Multiplexer/
Demultiplexer Chipset
Page 4
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
6/22/99
G52069-0, Rev. 4.1
VS8061 Phase Detector Logic Diagram
The phase detector inside the VS8061 compares the phase difference between the internally generated
divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in phase,
the U and D outputs will both be low. If the rising edge of CLK16 precedes DCLK, a series of pulses with pulse
widths proportional to the phase difference will be present at the U output. Conversely, if DCLK precedes
CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D output.
The other output will remain low. The Phase Detector ignores phase differences for falling edges. This circuitry
is useful for implementing a Clock Multiplier Unit (CMU) function with the VS8061. For example, the DLCK
can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator (VCO) at
16X the frequency of the reference clock can be used as the CLK input for the VS8061. The phase detector out-
puts (U and D) can then be used by an external integrator to generate an output that controls the VCO. The gen-
erated 16X clock from the VCO will be phase-locked to the reference clock.
Figure 4: VS8061 Phase Detector Logic Diagram
Figure 5: Phase Detector Input and Output Waveforms
CLK16
R
S
Q
S
RQ
U
D
DCLK
CLK16
DCLK
U
D
~ ~
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