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參數(shù)資料
| 型號(hào)： | VRG8692-201-2S |
| 元件分類(lèi)： | 可調(diào)正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器 |
| 英文描述： | 1 V-3.3 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.5 V DROPOUT, MDFM12 |
| 封裝： | 1 X 0.900 INCH, 0.220 INCH HEIGHT, HERMETIC SEALED, METAL, PACKAGE-12 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | VRG8692-201-2S |
6
SCD8691 Rev E 6/14/10
Aeroflex Plainview
VRG8691/92
VIN
VOUT
VSENSE
R1
R2
VREF (=1V)
CURR. LIMIT
10
11
12
4
3
2
1
8
ENABLE
6
9
IADJ
7
5
CLOAD
0.1F
47F
+
10F
VBIAS
SLOW START
VOUT
VBIAS
VIN
GND
0.1F
CDELAY
+
FIGURE 5 – DELAYED ENABLE
+
APPLICATION NOTE 3
START UP SEQUENCE
Recommended Power Supply Sequencing Options:
- OPTION 1: Controlling the ENABLE line with a Digital signal (TTL / CMOS compatible).
- Prior to applying power, disable the regulator by setting the ENABLE control line to a HIGH state.
- Apply VIN and VBIAS. 1/
- Wait until both VIN and VBIAS supplies have reached their operating levels.
- Toggle the ENABLE control line to a LOW state to turn on VOUT of the regulator.
- OPTION 2: Controlling the ENABLE line using the CDELAY feature.
- Connect a CDELAY capacitor between VBIAS and the ENABLE as shown in Figure 5 below. 2/
- Apply VIN and VBIAS. 1/
- CDELAY causes the regulator to self-enable after VBIAS has reached operating level.
NOTE: The ENABLE should always be asserted AFTER VIN and VBIAS have reached operating level.
NOTES:
1/ VIN should be applied before VBIAS if the Slow Start feature is used.
2/ CDELAY capacitor of 10uF is adequate for VBIAS rise times of up to 50ms.
1/
2/
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