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參數(shù)資料
| 型號： | VPX3214C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 6/80頁 |
| 文件大?。?/td> | 752K |
| 代理商： | VPX3214C |
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VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
6
2. Functional Description
2.1. Analog Front-End
This block provides the analog interfaces to all video in-
puts and mainly carries out analog-to digital conversion
for the following digital video processing. A block dia-
gram is given in Fig. 2–2.
Most of the functional blocks in the front-end are digitally
controlled (clamping, AGC, and clock-DCO). The con-
trol loops are closed by the Fast Processor (‘FP’) em-
bedded in the decoder.
2.1.1. Input Selector
Up to four analog inputs can be connected. They all must
be AC-coupled. Two of them (VIN2 and VIN3) are for in-
put of composite video or S-VHS luma signal. These in-
puts are clamped to the sync back porch and are ampli-
fied by a variable gain amplifier. One input (CIN) is for
connection of S-VHS carrier-chrominance signal. This
input is internally biased and has a fixed gain amplifier.
The fourth one (VIN1) can be used for both functions
(see Fig. 2–2). For possible combinations and types of
input signals, see Fig. 2–1.
CVBS
S-VHS
3
2
0
2
1
0
CVBS
Luma
Chroma
VIN1
VIN2
VIN3
CIN
Fig. 2–1:
Combinations and types of input signals
2.1.2. Clamping
The composite video input signals are AC-coupled to the
IC. The clamping voltage is stored on the coupling ca-
pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid-
eo signal. S-VHS chroma is also AC-coupled. The input
pin is internally biased to the center of the ADC input
range.
2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
o
i
clamp
level
bias/
clamp
DAC
freq.
frequ.
doubler
frequ.
divider
20.25 MHz
DAC
gain
ADC
AGC
+6/–4.5 dB
reference
generation
ADC
8
8
VIN3
level
select
Fig. 2–2:
Analog front-end
VIN2
VIN1
CIN
to
color
decoder
digital
chroma
digital
CVBS
or Y
system
clocks
DVCO
±
150
ppm
CVBS/Y
CVBS/Y
CVBS/
Y/C
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VPX3224D | Video Pixel Decoders |
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3214C(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3214C(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3216B(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
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