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參數(shù)資料
| 型號： | VP7610 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | COLOUR DIGITAL VIDEO CAMERA DECODER IC |
| 中文描述： | 彩色數(shù)字?jǐn)z像機(jī)解碼器IC |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 248K |
| 代理商： | VP7610 |
4
VP7610
Pin #
I/O
Name
Description
60
In*
CPCLK
Clock - This input receives the clock from the CamPort camera on port A.
54
In*
CPD3
CamPort Data Bit 3 - This bus receives the data from the CamPort camera on port
A.
55
In*
CPD2
CamPort Data Bit 2 - Port A
56
In*
CPD1
CamPort Data Bit 1 - Port A
59
In*
CPD0
CamPort Data Bit 0 - Port A
88
In*
CPCKB
CamPort B Clock - This input receives the clock from the CamPort camera on port
B.
84
In*
CPDB3
CamPort B Data Bit 3 - This bus receives the data from the CamPort camera on
port B.
85
In*
CPDB2
CamPort B Data Bit 2
86
In*
CPDB1
CamPort B Data Bit 1
87
In*
CPDB0
CamPort B Data Bit 0
91
Out
CPSEL
CamPort Select Status - When this output is low, the data from CamPort A is being
used, when this output is high, the data from CamPort B is being used. This pin is
controlled by Bit 3 of the Configuration Register (sub-address = 0x00)
.
44
In
RSTN
Reset Not - When this Schmidtt trigger input is low, the chip is placed into a known
state. When this input is high, the chip can operate.
11
Out
YY7
Luminance Out bit 7 - When CCSEL is low this bus carries the luminance data. When
CCSEL is high this bus carries multiplexed luminance and chrominance data
10
Out
YY6
Luminance Out bit 6
9
Out
YY5
Luminance Out bit 5
6
Out
YY4
Luminance Out bit 4
5
Out
YY3
Luminance Out bit 3
4
Out
YY2
Luminance Out bit 2
3
Out
YY1
Luminance Out bit 1
2
Out
YY0
Luminance Out bit 0
23
Out
UV7
Chrominance Out bit 7 - When CCSEL is low this bus carries the chrominance data.
When CCSEL is high this bus carries a constant value of 0x80 (128).
22
Out
UV6
Chrominance Out bit 6
21
Out
UV5
Chrominance Out bit 5
20
Out
UV4
Chrominance Out bit 4
17
Out
UV3
Chrominance Out bit 3
16
Out
UV2
Chrominance Out bit 2
15
Out
UV1
Chrominance Out bit 1
14
Out
UV0
Chrominance Out bit 0
24
Out
CLK2
Clock Out 2X - This clock runs at twice the pixel rate
27
Out
CLK1
Clock Out 1X - This clock runs at the pixel rate.
34
In
OUTEN
Output Enable - When this input is high, the signals YY[7..0], UV[7..0], HSYNC, VSYNC,
CLK2, CLK1, HACT, VACT, FIELD and BFLAG are driven. When this input is low,
these signals are high-impedance.
SIGNALS & PINOUT
* CamPort inputs are TTL levels. All other inputs are CMOS. See Static Electrical Characteristics table.
相關(guān)PDF資料 |
PDF描述 |
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| VP7610CGFPIR | COLOUR DIGITAL VIDEO CAMERA DECODER IC |
| VP7615CGFP1N | Video Camera Circuit |
| VP7615 | Colour Digital Video Camera Decoder IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP7610CGFPIR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:COLOUR DIGITAL VIDEO CAMERA DECODER IC |
| VP7615 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Colour Digital Video Camera Decoder IC |
| VP7615CGFP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Colour Digital Video Camera Decoder IC |
| VP-7710V-36001 | 制造商:Via Technologies, Inc 功能描述:- Bulk |
| VP-7710V-36121 | 制造商:VIA Technologies Inc 功能描述:- Bulk |
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