參數(shù)資料
型號: VP3203N8
廠商: SUPERTEX INC
元件分類: JFETs
英文描述: P-Channel Enhancement-Mode Vertical DMOS FETs
中文描述: Si, POWER, FET, TO-243AA
封裝: TO-243AA, 3 PIN
文件頁數(shù): 2/4頁
文件大?。?/td> 458K
代理商: VP3203N8
2
Package
I
D
(continuous)*
I
D
(pulsed)
Power Dissipation
@ T
A
= 25
°
C
0.74W
θ
jc
°
C/W
θ
ja
°
C/W
I
DR
*
I
DRM
TO-92
-0.65A
-4.0A
125
170
-0.65A
-4.0A
TO-243AA
-1.1A
-4.0A
1.6W
15
78
-1.1A
-4.0A
*
I
D
(continuous) is limited by max rated T
j
.
Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P
D
increase possible on ceramic substrate.
Electrical Characteristics
(@ 25
°
C unless otherwise specified)
VP3203
Thermal Characteristics
Switching Waveforms and Test Circuit
90%
10%
90%
90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
0V
V
DD
R
gen
0V
-10V
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
BV
DSS
V
GS(th)
V
GS(th)
I
GSS
I
DSS
Drain-to-Source Breakdown Voltage
-30
V
V
GS
= 0V, I
D
= -10mA
V
GS
= V
DS
, I
D
= -10mA
V
GS
= V
DS
, I
D
= -10mA
V
GS
=
±
20V, V
DS
= 0V
V
GS
= 0V, V
DS
= Max Rating
V
GS
= 0V, V
DS
= 0.8 Max Rating
T
A
= 125
°
C
V
GS
= -10V, V
DS
= -5V
V
GS
= -4.5V, I
D
= -1.5A
V
GS
= -4.5V, I
D
= -0.75A
V
GS
= -10V, I
D
= -3A
V
GS
= -10V, I
D
= -1.5A
V
GS
= -10V, I
D
= -1.5A
V
DS
= -25V, I
D
= -2A
Gate Threshold Voltage
-1.0
-3.5
V
Change in V
GS(th)
with Temperature
Gate Body Leakage
-5.5
mV/
°
C
-1.0
-100
nA
Zero Gate Voltage Drain Current
-10
μ
A
-1
mA
I
D(ON)
R
DS(ON)
ON-State Drain Current
-14
A
TO-92
1.0
SOT-89
1.0
TO-92
0.6
SOT-89
0.6
R
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Change in R
DS(ON)
with Temperature
Forward Transconductance
1.0
%/
°
C
1.0
2.0
Input Capacitance
200
300
Common Source Output Capacitance
100
120
pF
Reverse Transfer Capacitance
45
60
Turn-ON Delay Time
10
Rise Time
15
Turn-OFF Delay Time
25
Fall Time
25
Diode Forward Voltage Drop
-1.6
V
V
GS
= 0V, I
SD
= -1.5A
V
GS
= 0V, I
SD
= -1A
Reverse Recovery Time
300
ns
Notes
:
1. All D.C. parameters 100% tested at 25
°
C unless otherwise stated. (Pulse test: 300
μ
s pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
ns
V
GS
= 0V, V
DS
= -25V
f = 1 MHz
V
DD
= -25V
I
D
= -2A
R
GEN
= 10
Static Drain-to-Source
ON-State Resistance
相關PDF資料
PDF描述
VP3203ND P-Channel Enhancement-Mode Vertical DMOS FETs
VP5002BJ111H00 VP50 PROPORTIONAL VALVE
VP5002BJ411H00 VP50 PROPORTIONAL VALVE
VP5006BJ111H00 VP50 PROPORTIONAL VALVE
VP5006BJ411H00 VP50 PROPORTIONAL VALVE
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