參數(shù)資料
型號(hào)： VNC2-64Q1B-TRAY
廠商： FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù)： 33/88頁(yè)
文件大?。?/td> 0K
描述： IC USB HOST/DEVICE CTRL 64-QFN
應(yīng)用說明： Vinculum-II IO Cell Description AppNote
Vinculum-II Debug Interface Description AppNote
Vinculum-II IO Mux Explained AppNote
Vinculum-II PWM Example AppNote
Migrating Vinculum Designs AppNote
標(biāo)準(zhǔn)包裝： 260
系列： Vinculum-II
控制器類型： USB 2.0 控制器
接口： USB，主機(jī)/設(shè)備配置，UART，SPI，PWM，閃存 256K，DMA 4CH
電源電壓： 1.62 V ~ 1.98 V
電流 - 電源： 25mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（8x8）
包裝： 托盤
其它名稱： VNC2-64Q1A-TRAY
VNC2-64Q1A-TRAY-ND
39
Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
6.2 Serial Peripheral Interface – SPI Modes
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
VNC2 has one master module and two slave modules. Each SPI slave module has four signals – clock,
slave select, MOSI (master out – slave in) and MISO (master in – slave out). The SPI Master has the
same four signals as the slave modules but with one additional signal because it requires a slave select
for the second slave module. Table 6.2 lists how the signals are named in each module.
The SPI Master clock can operate up to one half of the CPU system clock depending on what power mode
the device is set to:
Normal power mode 48Mhz would set the SPI maximum clock to 24Mhz
Low power mode 24Mhz would set the SPI maximum clock to 12Mhz
Lowest power mode 12Mhz would set the SPI maximum clock to 6hMz
Module
Signal Name
Type
Description
SPI Slave
0
spi_s0_clk
Input
Clock input – slave 0
spi_s0_ss#
Input
Active low chip select input – slave 0
spi_s0_mosi
Input
Master out serial in – slave 0
spi_s0_miso
Output
Master in slave out – slave 0
SPI Slave
1
spi_s1_clk
Input
Clock input – slave 1
spi_s1_ss#
Input
Active low chip select input – slave 1
spi_s1_mosi
Input
Master out slave in – slave 1
spi_s1_miso
Output
Master in slave out – slave 1
SPI Master
spi_m_clk
Output
Clock output – master
spi_m_mosi
Output
Master out slave in - master
spi_m_miso
Input
Master in slave out - master
spi_m_ss_0#
Output
Active low slave select 0 from master to slave 0
spi_m_ss_1#
Output
Active low slave select 1 from master to slave 1
Table 6.2 SPI Signal Names
The SPI slave protocol by default does not support any form of handshaking. FTDI have added extra
modes to support handshaking, faster throughput of data and reduced pin count. There are 5 modes
(Table 15) of operation in the VNC2 SPI Slave.
Full Duplex – Section 0
Half Duplex, 4 pin - Section 6.3.3
Half Duplex, 3 pin - Section 6.3.4
Unmanaged - Section 6.3.5
VNC1L legacy mode – Section 6.3.6
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