參數(shù)資料
型號: VNC2-48Q1B-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 59/88頁
文件大小: 0K
描述: IC USB HOST/DEVICE CTRL 48-QFN
應用說明: Vinculum-II IO Cell Description AppNote
Vinculum-II Debug Interface Description AppNote
Vinculum-II IO Mux Explained AppNote
Vinculum-II PWM Example AppNote
Migrating Vinculum Designs AppNote
特色產(chǎn)品: Vinculum VNC2
標準包裝: 1
系列: Vinculum-II
控制器類型: USB 2.0 控制器
接口: USB,主機/設備配置,UART,SPI,PWM,閃存 256K,DMA 4CH
電源電壓: 1.62 V ~ 1.98 V
電流 - 電源: 25mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應商設備封裝: 48-QFN-EP(8x8)
包裝: 標準包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
其它名稱: 768-1048-6
62
Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
6.7.1 Read / Write Transaction Synchronous FIFO Mode
When in Synchronous FIFO interface mode, the timing of read and write operations on the FIFO interface
In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An
external device synchronises to the CLKOUT output and it also has access to the output enable OE# input
to control data flow. An external device should drive output enable OE# low before pulling RD# line
down.
When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when
there is still data to be read. Similarly when bursts of data are to be written to the module WR# should
be kept low. TXE# remains low when there is still space available for the data to be written.
Figure 6.23 Synchronous FIFO mode Read / Write Cycle
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