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| 型號： | VIC64-UC |
| 英文描述： | VME/VMS/VXI/VSB Bus Interface/Controller |
| 中文描述： | VME總線/威邁斯/ VXI總線/獸醫(yī)管理局總線接口/控制器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 833K |
| 代理商： | VIC64-UC |
VIC64
Document #: 38-09002 Rev. **
Page 5 of 13
Functional Description (continued)
The VIC64 supports A32, A24, and A16, as well as
user-defined address spaces.
Master Write-Posting
The VIC64 is capable of performing master write-posting (bus
decoupling). In this situation, the VIC64 acknowledges the
local resource immediately after the request to the VIC64 is
made, thus freeing the local bus. The VIC64 latches the local
data to be written and performs the VMEbus transfer without
the local resource having to wait for VMEbus arbitration.
Indivisible Cycles
Read-modify-write cycles and indivisible multiple-address
cycles (IMACs) are easily performed using the VIC64.
Significant control is allowed for:
Requesting the VMEbus on the assertion of RMC indepen-
dent of MWB* (this prevents any slave access from inter-
rupting local indivisible cycles)
Stretching the VMEbus AS*
Making the above behaviors dependent on the local SIZi
signals
Deadlock
If a master operation is attempted when a slave operation to
the same module is in progress, a deadlock condition occurs.
The VIC64 signals a deadlock condition by asserting the
DEDLOCK* signal. This should be used by the local resource
requesting the VMEbus to try the transfer after the slave
access has completed.
Self-Access
If the VIC64, while it is VMEbus master, has a slave select
signaled, a self-access has occurred. The VIC64 asserts
BERR* and LBERR*.
VIC64 VMEbus Slave Cycles
The VIC64 is capable of operating as a VMEbus slave
controller. The VIC64 contains a highly programmable
environment to allow for a wide variety of slave configurations.
The VIC64 allows for:
D64, D32, D16, or D8 configuration
A32, A24, A16, or user-defined address spaces
Programmable block transfer support including:
— DMA-type block transfer (PAS* and DSACKi* held
asserted)
— Non DMA-type block transfer (toggle PAS&* and
DSACKi*)
— No support for block transfer
Programmable data acquisition delays
Programmable PAS* and DS* timing
Restricted slave accesses (supervisory accesses only)
When a slave access is required, the VIC64 requests the local
bus. When local bus mastership is obtained, the VIC64 reads
or writes the data to/from the local resource and asserts the
DTACK* signal to complete the transfer.
Slave Write-Posting
The VIC64 is capable of performing a slave write-post
operation (bus decoupling). When enabled, the VIC64 latches
the data to be written, and acknowledges the VMEbus (asserts
DTACK*) immediately thereafter. This prevents the VMEbus
from having to wait for local bus access.
Address Modifier (AM) Codes
The VIC64 encodes and decodes the VMEbus address
modifier codes. For VMEbus master accesses, the VIC64
encodes the appropriate AM codes through the VIC64 FCi and
ASIZi signals, as well as the block transfer status. For slave
accesses, the VIC64 decodes the AM codes and checks the
slave select control registers to see if the slave request is to be
supported with regard to address spaces, supervisory
accesses, and block transfers. The VIC64 also supports
user-defined AM codes; that is, the VIC64 can be made to
assert and respond to user-defined AM codes.
VIC64 VMEbus Block Transfers
The VIC64 is capable of both master and slave block transfers.
The master VIC64 performs a block transfer in one of two
modes:
The Master Block Transfer with Local DMA (D16, D32, and
D64)
The MOVEM-type Block Transfer (D16 and D32)
In addition to these VMEbus block transfers, the VIC64 is also
capable of performing block transfers from one local resource
to another in a DMA-like fashion. This is referred to as a
module-based DMA transfer.
For D32 block transfers, the VMEbus specification restricts
block transfers from crossing 256-byte boundaries without
toggling the address strobe, in addition to restricting the
maximum length of the transfer to 256 bytes. The VIC64 allows
for easy implementation of block transfers that exceed the
256-byte restriction by releasing the VMEbus at the
appropriate time and re-arbitrating for the bus at a
programmed time later (this in-between time is referred to as
the interleave period), while at the same time holding both the
local and VMEbus addresses with internal latches. All of this
is performed without processor/software intervention until the
transfer is complete. For D64 block transfers, the VMEbus
specification allows for bursts of up to 2048 bytes.
The VIC64 contains two separate address counters for the
VMEbus and local address buses. In addition, a separate
address counter is provided for slave block transfers. The
VIC64 address counters are 8-bit up-counters that provide for
transfers up to 256 bytes. For transfers that exceed the 256
byte limit, the external counters and latches are required.
The VIC64 is capable of performing A32/A16:D64/D32/D16
master block transfers. For D64 transfers, external logic is
required for the multiplexing of the data and address signals
for the upper 24 address/data lines. The CY7C964 is
specifically designed for this purpose. Multiplexing for the
lower 8 bits is done within the VIC64.
The VIC64 allows slave accesses to occur during the
interleave period. Master accesses are also allowed during
interleave with programming and external logic. This is
referred to as the dual-path option.
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