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7
VFC110
reset current. The equation of current balance is
I
IN
= I
REF
Duty Cycle
V
IN
/R
IN
= I
REF
f
OUT
T
O
where T
is the one-shot period and f
OUT
is the oscillation
frequency.
Integrator
Output
(Pin 12)
0V
f
OUT
1/f
OUT
T
OS
Effect of
Smaller C
INT
When the Enable input receives a logic High (greater than
+2V), a reset current cycle is initiated (causing f
OUT
to go
Low). The integrator ramps positively and normal operation
is established. The time required for the output frequency to
stabilize is equal to approximately one cycle of the final
output frequency plus 1
μ
s.
Using the Enable input, several VFCs’ outputs can be con-
nected to a single output line. All disabled VFCs will have a
high output impedance; one active VFC can then transmit on
the output line. Since the disabled VFCs are not oscillating,
they cannot interfere or “l(fā)ock” with the operating VFC.
Locking can occur when one VFC operates at nearly the
same frequency as—or a multiple of—a nearby VFC.
Coupling between the two may cause them to lock to the
same or exact multiple frequency. It then takes a small
incremental input voltage change to unlock them. Locking
cannot occur when unneeded VFCs are disabled.
REFERENCE VOLTAGE
The V
REF
output is useful for offsetting the transfer function
and exciting sensors. Figure 3 shows V
REF
used to offset the
transfer function of the VFC110 to achieve a bipolar input
voltage range. Sub-surface zener reference circuitry is used
for low noise and excellent temperature drift. Output current
is specified to 10mA and current-limited to approximately
20mA. Excessive or variable loads on V
REF
can decrease
frequency stability due to internal heating.
MEASURING THE OUTPUT FREQUENCY
To complete an integrating A/D conversion, the output
frequency of the VFC110 must be counted. Simple fre-
quency counting is accomplished by counting output pulses
for a reference time (usually derived from a crystal oscilla-
PRINCIPLE OF OPERATION
The VFC110 uses a charge-balance technique to achieve
high accuracy. The heart of this technique is an analog
integrator formed by the integrator op amp, feedback
capacitor C
, and input resistor R
. The integrator’s
output voltage is proportional to the charge stored in C
INT
.
An input voltage develops an input current of V
/R
,
which is forced to flow through C
. This current charges
C
, causing the integrator output voltage to ramp nega-
tively.
When the output of the integrator ramps to 0V, the
comparator trips, triggering the one-shot. This connects
the reference current, I
REF
, to the integrator input during
the one-shot period, T
integrator output to ramp positively until the one-shot
period ends. Then the cycle starts again.
The oscillation is regulated by the balance of current (or
charge) between the input current and the time-averaged
FIGURE 3. Offsetting the Frequency Output.
2
NC
IN
V
1
12
11
One-Shot
V
REF
4
13
5V
3
6
8
OUT
f
7
5
PU
R
C
OS
R
1
14
NC
+5V
+15V
10
–15V
R
2