6
VFC110
The integrator capacitor’s value does not directly affect the
output frequency, but determines the magnitude of the volt-
age swing on the integrator’s output. Using a C
INT
equal to
C
OS
provides an integrator output swing from 0V to approxi-
mately 1.5V.
COMPONENT SELECTION
Selection of the external resistor and capacitor type is impor-
tant. Temperature drift of an external input resistor and one-
shot capacitor will affect temperature stability of the output
frequency. NPO ceramic capacitors will normally produce
the best results. Silver-mica types will result in slightly
higher drift, but may be adequate in many applications. A
low temperature coefficient film resistor should be used for
R
IN
.
The integrator capacitor serves as a “charge bucket,” where
charge is accumulated from the input, V
IN
, and that charge is
drained during the one-shot period. While the size of the
bucket (capacitor value) is not critical, it must not leak.
Capacitor leakage or dielectric absorption can affect the
linearity and offset of the transfer function. High-quality
ceramic capacitors can be used for values less than 0.01
μ
F.
Use caution with higher value ceramic capacitors. High-k
ceramic capacitors may have voltage nonlinearities which
can degrade overall linearity. Polystyrene, polycarbonate, or
mylar film capacitors are superior for high values.
PULL-UP RESISTOR
The VFC110’s frequency output is an open-collector transis-
tor. A pull-up resistor should be connected from f
OUT
to the
logic supply voltage, +V
L
. The output transistor is On during
the one-shot period, causing the output to be a logic Low.
The current flowing in this resistor should be limited to 8mA
to assure a 0.4V maximum logic Low. The value chosen for
the pull-up resistor may depend on the full-scale frequency
and capacitance on the output line. Excessive capacitance on
f
OUT
will cause a slow, rounded rising edge at the end of an
output pulse. This effect can be minimized by using a pull-
up resistor which sets the output current to its maximum of
8mA. The logic power supply can be any positive voltage up
to +V
S
.
ENABLE PIN
If left unconnected, the Enable input will assume a logic
High level, enabling operation. Alternatively, the Enable
input may be connected directly to +V
S
. Since an internal
pull-up current is included, the Enable input may be driven
by an open-collector logic signal.
A logic Low at the Enable input causes output pulses to
cease. This is accomplished by interrupting the signal path
through the one-shot circuitry. While disabled, all circuitry
remains active and quiescent current is unchanged. Since no
reset current pulses can occur while disabled, any positive
input voltage will cause the integrator op amp to ramp
negatively and saturate at its most negative output swing of
approximately –0.7V.
FULL-SCALE
FREQUENCY, f
FS
R
IN
C
OS
C
INT
4MHz
2MHz
1MHz
500kHz
100kHz
50kHz
10kHz
*
*
*
*
*
34k
40k
58k
44k
88k
44k
56pF
150pF
330pF
2.2nF
2.2nF
22nF
2nF
10nF
0.1
μ
F
0.1
μ
F
* Use internal component only.
The values given were determined empirically to give the optimal perform-
ance, taking into consideration tradeoffs between linearity and jitter for each
given full scale frequency of operation. The capacitors listed were chosen
from standard values of NPO ceramic type capacitors while the resistor
values were rounded off. Larger C
INT
values may improve linearity, but may
also increase frequency noise.
EXTERNAL COMPONENTS
TABLE I. Component Selection Table.
FIGURE 2. 100kHz Full-Scale Operation.
2
IN
V
1
12
11
One-Shot
V
REF
–V
S
4
13
NC
3
6
8
OUT
f
10
+V
S
7
5
PU
R
+V
L
0 to 100kHz
C
2.2nF
High = Enable
Low = Disable
10nF
C
INT
0 to +10V
Gain Trim
5k
44k
R
IN
NC
14