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參數資料
| 型號： | VDD7616A4A-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DOUBLE DATA RATE SDRAM |
| 中文描述： | 雙倍數據速率SDRAM內存 |
| 文件頁數： | 3/9頁 |
| 文件大小： | 548K |
| 代理商： | VDD7616A4A-75B |
V-Data
VDD7616A4A
Pin Description
PIN
NAME
FUNCTION
CK, /CK
System Clock
Differential clock input.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
A0~A11
Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A11
Column address : A0~A8
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ15 Data
Data inputs / outputs are multiplexed on the same pins.
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS
low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers.
VREF
Reference Voltage
Reference voltage for inputs for SSTL interface.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
Command
Decoder
CK
/CK
CKE
/CS
/RAS
/CAS
/WE
LDM
UDM
Address
Buffer
A0 ~ A11
Bank
Control
1
Mx32/Bank0
Column Decoder
Column Address
Counter
S
2
1
Mx32/Bank1
Mx32/Bank2
1
Mx32/Bank3
Mode
Register
Row
Decoder
I
O
DLL
Block
Mode
Register
Data Strobe
Transmitter
Data Strobe
Receiver
LDQS, UDQS
CLK
DS
Write Data Register
2-bit Prefetch Unit
DS
DQ[0:15]
32
16
16
32
CLK_DLL
BA0, BA1
Rev 2 Apr, 2002
3
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