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參數(shù)資料
| 型號(hào)： | VCLGCAAT38.880MHZ |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 38.88 MHz, CMOS/TTL OUTPUT |
| 封裝： | HERMETICALLY SEALED, CERAMIC, LCC-6 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | VCLGCAAT38.880MHZ |
V-Type Voltage Controlled Crystal Oscillator (VCXO)
Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON
Pin Information
Table 1.
1
Vc
Control Voltage.
22
TTL/CMOS1
TTL logic low for CMOS optimized symmetry
TTL logic high or no connection for TTL optimized symmetry.
3
GND
Case/circuit ground.
4
Output
Output waveform.
52
Tri-state
TTL logic low diables output.
TTL logic high or no connection enables output waveform.
6VDD
Supply Voltage, 5 V ±10%, or 3.3V ±10%
Pin #
Symbol
Name/Function
1. This silicon oscillator is fabricated in CMOS technology and
its output waveform will swing between ground and VDD for
all but the highest frequency applications. To account for the
difference in switching thresholds between TTL logic (1.40 V)
and CMOS logic (VDD/2), the TTL/CMOS lead modifies the
“on time” of the oscillator for maximum symmetry about the
TTL or CMOS logic threshold. TTL logic low provides wave-
form symmetry for CMOS. TTL logic high or no connection pro-
vides waveform symmetry for TTL. At output frequencies less
than 12 MHz, this option is not provided as the waveform tran-
sition times are small compared to the period. Hence, for fo
<12 MHz this pin should be grounded for electrical isolation.
2. Alternate Pin Configuration for Tri-state Control on Pin 2
and TTL/CMOS on pin 5. Alternate Configuration is indicated
by last letter of part code “D” for TriState Pin 2 and TTL/CMOS
on pin 5.
Table 2. Performance Specifications
1 A 0.1 uF low frequency tantalum bypass capacitor in parallel with a
0.01 uF high-frequency ceramic capacitor is recommended.
2 Figure 1 defines these parameters. Figure 2 illustrates the equiva-
lent five-gate MTTL load and operating conditions under which
these parameters are specified.
3 Symmetry is defined as (ON TIME/PERIOD), with VS = 1.4 V for
TTL or VS = 2.5 V for CMOS. per Figure 1.
Supply Voltage’ (5V or 3.3V)
VDD
0.9*VDD
1.1*VDD
V
Supply Current (Frequency Dependent)
IDD
See Figures 7,8
mA
OutputVoltage Levels (VDD = 4.5V):
Output Logic High 2
VOH
0.8*VDD
-V
Output Logic Low 2
VOL
-
0.1*VDD
V
Transition Times 2:
Rise Time
tR
5ns
Fall Time
tF
5ns
Symmetry or Duty Cycle3
SYM
See figure 3, 4
%
Nominal Output Frequency (see ordering info)
fo
1.024
77.760
MHz
Control Voltage (5v), test conditions for APR
Vc
0.5
4.5
V
Control Voltage (3.3v), test conditions for APR
Vc
0.3
3.0
V
Control Voltage
Vc
0VDD
V
Absolute Pull Range (see ordering info)
APR
±20 to ±100
Leakage Current of Control Input
Ivcxo
-1.0
1.0
uA
Control Voltage Bandwidth (-3 dB,VC=2.50V)
BW
10
-
kHz
Parameter
Symbol
Min
Max
Unit
2
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