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參數(shù)資料
| 型號： | VCC1-E2O-16M384 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 16.384 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, SMD, 4 PIN |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 179K |
| 代理商： | VCC1-E2O-16M384 |
VCC1 Data sheet
Vectron International 267 Lowell Rd, Hudson NH 03051
Tel: 1-88-VECTRON-1
e-mail: vectron@vectron.com
Table 4. Electrical Performance, 1.8V option
Parameter
Symbol
Min
Typical
Maximum
Units
Frequency
fO
0.048
172.000
MHz
Operating Supply Voltage
1
VDD
1.71
1.8
1.89
V
Absolute Maximum Voltage
-0.5
3.6
V
Supply Current, Output Enabled
< 20 MHz
20.01 to 70 MHz
70.01 to 96 MHz
96.01 to 125 MHz
125.01 to 172 MHz
IDD
5
15
20
25
30
mA
Supply Current, Out disabled
IDD
30
uA
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Logic High Drive
Output Logic Low Drive
Output Logic High Drive
3
Output Logic Low Drive
3
VOH
VOL
IOH
IOL
IOH
IOL
0.9*VDD
2.8
8
0.1*VDD
V
mA
Output Rise/Fall Time
2
< 1.00 MHz
1.000 to 20.00 MHz
20.01 to 50.00 MHz
50.01 to 90.00 MHz
90.01 to 172.00 MHz
tR/tF
200
4
3
2
ns
Duty Cycle
4 (ordering option)
SYM
45/55
%
Operating temperature (ordering option)
-10/70 or –40/85
°C
Storage Temperature
-55
125
°C
Stability
5 (ordering option)
±20, ±25, ±32, ±50, ±100
ppm
RMS Jitter, 12kHz to 20 MHz
0.5
ps
RMS Jitter
2.2
ps
Output Enable/Disable
6
Output Enabled
Output Disabled
1.26
0.5
V
Internal Enable Pull-Up resistor
6
1
Mohm
Start-up time
10
ms
1. A 0.01uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground) is recommended.
2. Figure 7 defines these parameters. Figure 8 illustrates the operating conditions under which parameters are tested/specified.
3. Overtone designs, output frequencies>35MHz.
4. Symmetry is measured defined as On Time/Period.
5. Includes calibration tolerance, operating temperature, supply voltage variations, aging and shock and vibration (not under
operation).
6. Output will be enabled if enable/disable is left open.
Figure 7. Output Waveform
Figure 8. Typical Output Test Conditions (25
±5°C)
80
%
Vs
20
%
t
F
t
R
Period
On Time
+
-
+
-
IC
VC
3
2
.1F
.01
F
15pF
4
1
IDD
VDD
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