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參數(shù)資料
| 型號(hào)： | VC-801-JAE-SABN-44M0000000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 44 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-4 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 0K |
| 代理商： | VC-801-JAE-SABN-44M0000000 |
Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 http://www.vectron.com
Page6
Typical Characteristics - Phase Noise and Gain Curve
Outline Drawing & Pad Layout
Table 5. Pin Out
Pin
Symbol
Function
1
E/D
Enable Disable
2
GND
Case and Electrical Ground
3
Output
4
V
DD
Power Supply Voltage
Dimensions in mm
FREQUENCY
Date Code
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow
simulation. The VC-801 family is capable of meeting the following qualification tests:
Table 6. Environmental Compliance
Parameter
Conditions
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solvents
MIL-STD-883, Method 2015
Moisture Sensitivity Level
MSL 1
Contact Pads
Gold over Nickel
Table 7. ESD Ratings
Model
Minimum
Conditions
Human Body Model
1500V
MIL-STD-883, Method 3015
Charged Device Model
1000V
JESD22-C101
Although ESD protection circuitry has been designed into the VC-801 proper precautions should be taken when handling
and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing
and design protection evaluation.
Table 8. Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Storage Temperature
T
S
-55 to 125
°C
Soldering Temp/Time
T
LS
260 / 20
°C / sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not
implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.
Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is
also possible if E/D is applied before V
DD
.
2.54
1.4
1.2
2.2
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