參數(shù)資料
型號: V85C2256164SAS8
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 16M X 16 DDR DRAM, 0.8 ns, PBGA60
封裝: 0.80 X 1 MM PITCH, SOC, BGA-60
文件頁數(shù): 19/61頁
文件大小: 814K
代理商: V85C2256164SAS8
26
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
QFC function
when driven low on reads coincident with the start of preamble, this DRAM output signal says that one cy-
cle later there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is
also driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe
transition is received. Whenever the device is in standby, the signal is HI-Z. DQS is intended to enable an
external data switch. QFC can be enabled or disabled through EMRS control.
QFC timing on Read operation
QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end
of DQS postamble
Figure 26. QFC timing on read operation
Command
2
01
5
34
8
67
Read
Dout 0
Dout 1
Hi-Z
DQS
DQ’S
QFC
tQPRE
tQPST
CL = 2, BL = 2
CK
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