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參數(shù)資料
| 型號： | V62C518256LL-70P |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 8 STATIC RAM(54.75 k |
| 中文描述： | 32K的× 8靜態(tài)RAM（54.75畝 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 54K |
| 代理商： | V62C518256LL-70P |
8
V62C518256 Rev. 2.3 November 1998
MOSEL V ITELIC
V62C518256
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)
(4)
Write Cycle 2 (CE Controlled)
(4)
NOTES:
1.
The internal write time of the memory is defined by the overlap of CE active and WE low. Both signals must be active to initiate and
any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
t
WR
is measured from the earlier of CE or WE going HIGH.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
OE = V
IL
or V
IH
. However it is recommended to keep OE at V
IH
during write cycle to avoid bus contention.
If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied to them.
t
CW
is measured from CE going LOW to the end of write.
2.
3.
4.
5.
6.
ADDRESS
OUTPUT
INPUT
CE
WE
518256-11
t
WC
t
CW(6)
t
DW
t
DH
t
AW
t
WR(2)
t
WHZ(3)
t
WP(1)
t
AS
ADDRESS
OUTPUT
INPUT
CE
WE
518256-12
t
WC
t
DW
t
DH
t
AW
t
WR(2)
Hi-Z
t
AS
(5)
t
CW(6)
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