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參數(shù)資料
| 型號： | V62C518256 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 8 STATIC RAM |
| 中文描述： | 32K的× 8靜態(tài)RAM |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 54K |
| 代理商： | V62C518256 |
2
V62C518256 Rev. 2.3 November 1998
MOSEL V ITELIC
V62C518256
Pin Descriptions
A
These 15 address inputs select one of the 32,768 x
8 bit segments in the RAM.
0
–A
14
Address Inputs
CE
CE is an active LOW input. Chip Enable must be
LOW when reading from or writing to the device.
When HIGH, the device is in standby mode with I/O
pins in the high impedance state.
Chip Enable Inputs
OE
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
Output Enable Input
WE
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
Write Enable Input
I/O
These 8 bidirectional ports are used to read data
from and write data into the RAM.
0
–I/O
7
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
28-Pin DIP/SOP
28-Pin TSOP (Standard)
V
CC
A
8
A
9
A
11
OE
A
10
I/O
0
I/O
1
I/O
2
GND
A
0
A
1
A
2
A
3
A
4
A
5
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
518256-01
A
13
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
14
A
12
A
6
A
7
CE
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
518256-03
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