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參數(shù)資料
| 型號： | V62C3802048LL-45BI |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 8 STANDARD SRAM, 45 ns, PBGA48 |
| 封裝： | 9 X 12 MM, CSP, FBGA-48 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | V62C3802048LL-45BI |
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8
9
16
15
14
13
12
11
10
A8
A9
A11
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
32
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27
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17
18
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23
CE1
A10
OE
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
Cell Array
ROW
DECODER
SENSE
AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
A8
A7
A6
A5
A4
A3
A2
A1
A0
A9
A10
A11
A12
A13
A14
A15
A16 A17
V62C3802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
Low-power consumption
- Active: 40mA at 35ns
- Stand-by: 10
A (CMOS input/output)
2
A CMOS input/output, L version
Single + 2.7 to 3.3V Power Supply
Equal access and cycle time
35/45/55/70/85/100 ns access time
Easy memory expansion with CE1, CE2
and OE inputs
1.0V data retention mode
TTL compatible, Tri-state input/output
Automatic power-down when deselected
Package available: 32-TSOP1 / STSOP
48 Ball CSP_BGA
Functional Description
The V62C3802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1, an active HIGH CE2, an acti-
ve LOW OE , and Tri-state I/O’s. This device has an autom-
atic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip En-
able 1 (CE1) with Write Enable (WE ) LOW, and Chip Enab-
le 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance sta-
te when the device is deselected: the outputs are disabled d-
uring a write cycle.
The V62C3802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C3802048L is available in
a 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type
48-fpBGA packages.
32-Pin TSOP1 / STSOP(CSP_BGA see next page)
Logic Block Diagram
REV. 1.2 May 2001 V62C3802048L(L)
1
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