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參數(shù)資料
| 型號： | V62C31864L-35F |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 STANDARD SRAM, 35 ns, PDSO28 |
| 封裝： | 0.330 INCH, SOP-28 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 68K |
| 代理商： | V62C31864L-35F |
MOSEL VITELIC
1
V62C31864
2.7 VOLT 8K X 8 STATIC RAM
PRELIMINARY
V62C31864 Rev. 1.6 August 1998
Features
s High-speed: 35, 70 ns
s Ultra low DC operating current of 2mA (Max.)
s Low Power Dissipation:
– TTL Standby: 1 mA (Max.)
– CMOS Standby: 10
mA (Max.)
s Fully static operation
s All inputs and outputs directly compatible
s Three state outputs
s Ultra low data retention current (VCC = 2V)
s Extended operating voltage: 2.7V–3.6V
s Packages
– 28-pin TSOP (Standard)
– 28-pin 300 mil SOP (450 mil pin-to-pin)
Description
The V62C31864 is a 65,536-bit static random
access memory organized as 8,192 words by 8
bits. It is built with MOSEL VITELIC’s high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
F
35
70
L
LL
0
°C to 70 °C
Blank
–40
°C to +85°C
I
Functional Block Diagram
Row
Decoder
512 x 128
Memory Array
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
VCC
GND
A0
31864 01
A8
I/O0
I/O7
CE2
OE
WE
CE1
A9
A12
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