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參數(shù)資料
| 型號： | V62C3184096L-55T |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP-32 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 52K |
| 代理商： | V62C3184096L-55T |
MOSEL V ITELIC
1
V62C3184096
512K X 8, CMOS STATIC RAM
PRELIMINARY
V62C3184096 Rev. 1.1 June 2000
Features
I
High-speed: 55, 70 ns
I
Ultra low standby current of 5
I
Fully static operation
I
All inputs and outputs directly compatible
I
Three state outputs
I
Ultra low data retention current (V
I
Operating voltage: 2.7V–3.3V
I
Packages
– 32-Pin TSOP (Standard)
– 36-Ball CSP BGA (8mm x 10mm)
μ
A (max.)
CC
= 2.0V)
Description
The V62C3184096 is a very low power CMOS
static RAM organized as 524,288 words by 8 bits.
Easy memory expansion is provided by an active
LOW CE1, and active HIGH CE2, an active LOW
OE, and three static I/O’s. This device has an
automatic power-down mode feature when
deselected.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
B
55
70
L
LL
0
°
C to 70
°
C
Blank
–40
°
C to +85
°
C
I
Functional Block Diagram
R
S
1024
x
4096
Column Decoder
Input Buffer
Control
Circuit
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
I/O1
I/O
8
OE
WE
CE1
CE2
A
17
A
18
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