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參數資料
| 型號： | V62C3162048LL-100T |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | Ultra Low Power 128K x 16 CMOS SRAM |
| 中文描述： | 128K的超低功耗× 16 CMOS SRAM的 |
| 文件頁數： | 10/13頁 |
| 文件大小： | 109K |
| 代理商： | V62C3162048LL-100T |
10
Notes
(Write Cycle)
1.
2.
All write timing is referenced from the last valid address to the first transition address.
A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going
low: A write ends at the earliest transition among CE going high and WE going high.
t
WP
is measured from the beginning
of write to the end of write.
3.
t
CW
is measured from the later of CE going low to end of write.
4.
t
AS
is measured from the address valid to the beginning of write.
5.
t
WR
is measured from the end of write to the address change.
6.
If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
7.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8.
If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
9.
D
OUT
is the read data of the new address.
10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should
not be applied.
11. For test conditions, see
AC Test Condition
, Figure A.
V62C31620
48
L(L)
REV. 1.
2
May
2001 V62C
3
1620
48
L(L)
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