參數(shù)資料
型號(hào): V62C2801024L(L)-70B
廠商: Mosel Vitelic, Corp.
英文描述: Ultra Low Power 128K x 8 CMOS SRAM
中文描述: 128K的超低功耗× 8 CMOS SRAM的
文件頁數(shù): 5/10頁
文件大?。?/td> 92K
代理商: V62C2801024L(L)-70B
V62C2801024L(L)
Parameter
Symbol
Unit
Note
Read Cycle Time
t
RC
70
-
85
-
100
-
150
-
ns
Address Access Time
t
AA
-
70
-
85
-
100
-
150
ns
Chip Enable Access Time
t
ACE
-
70
-
85
-
100
-
150
ns
Output Enable Access Time
t
OE
-
40
-
40
-
50
-
70
ns
Output
Hold from
Address Change
t
OH
10
-
10
-
10
-
10
-
ns
Chip Enable to Output in Low-Z
t
CLZ
10
-
10
-
10
-
10
-
ns
4,5
Chip Disable to Output in High-Z
t
CHZ
-
30
-
35
-
40
-
50
ns
4,5
Output Enable to Output in Low-Z
t
OLZ
5
-
5
-
5
-
5
-
ns
4,5
Output
Disable to
Output in High-Z
t
OHZ
-
25
-
30
-
35
-
40
ns
4,5
Power-Up Time
t
PU
0
-
0
-
0
-
0
-
ns
5
Power-Down Time
t
PD
-
70
-
85
-
100
-
150
ns
5
Read Cycle
(3,9)
(V
cc
= 2.2 to 2.7V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Write Cycle
(3,11)
(V
cc
= 2.2 to 2.7V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Symbol
Unit
Note
Write Cycle Time
t
WC
70
-
85
-
100
-
150
-
ns
Chip Enable to Write End
t
CW
60
-
70
-
80
-
120
-
ns
Address Setup to Write End
t
AW
60
-
70
-
80
-
120
-
ns
Address Setup Time
t
AS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
50
-
60
-
70
-
100
-
ns
Write Recovering Time
t
WR
0
-
0
-
0
-
0
-
ns
Data Valid to Write End
t
DW
30
-
35
-
40
-
60
-
ns
Data Hold Time
t
DH
0
-
0
-
0
-
0
-
ns
Write Enable to Output in High-Z
t
WZ
-
30
-
35
-
40
-
50
ns
4,5
Output Active fromWrite End
t
OW
5
-
5
-
5
-
5
-
ns
4,5
Min Max Min Max Min Max Min Max
-70
-85
-100
5
Min Max Min Max Min Max Min Max
-70
-85
-100
-150
-150
REV. 1.
1
April
2001 V62C
2
801024L(L)
相關(guān)PDF資料
PDF描述
V62C2801024L(L)-85B Ultra Low Power 128K x 8 CMOS SRAM
V62C2801024L-150T Ultra Low Power 128K x 8 CMOS SRAM
V62C2801024L-150V Ultra Low Power 128K x 8 CMOS SRAM
V62C2801024L-70T Ultra Low Power 128K x 8 CMOS SRAM
V62C2801024L-70V Ultra Low Power 128K x 8 CMOS SRAM
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