參數(shù)資料
型號(hào): V62C18161024
廠商: Mosel Vitelic, Corp.
英文描述: 1.8 Volt 128K x 16 Static RAM(1.8V 128Kx16靜態(tài)RAM)
中文描述: 1.8伏128K的× 16靜態(tài)RAM(1.8 128Kx16靜態(tài)內(nèi)存)
文件頁數(shù): 2/10頁
文件大小: 61K
代理商: V62C18161024
2
V62C18161024 Rev. 0.1 February 1999
MOSEL V ITELIC
V62C18161024
Pin Descriptions
A
These 16 address inputs select one of the 128K x
16 bit segments in the RAM.
0
–A
16
Address Inputs
CE, CE2*
CE is active LOW. CE2 is active High. It must be
active to read from or write to the device. If chip
enable is not active, the device is deselected and is
in a standby power mode. The I/O pins will be in
the high-impedance state when deselected.
Chip Enable Inputs
OE
The output enable input is active LOW. When OE
is Low with CE Low and WE High, data will be pre-
sented on the I/O pins. The I/O pins will be in the
high impedance state when OE is High.
Output Enable Input
UBE, LEB
Active low inputs. These inputs are used to enable
the upper or lower data byte.
Byte Enable
WE
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
Write Enable Input
I/O
These 16 bidirectional ports are used to read data
from and write data into the RAM.
0
–I/O
15
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
A16
A5
A6
A7
OE
UBE
LBE
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
CE2/NC*
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
18161024-02
44-Pin TSOP-II
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