參數(shù)資料
型號(hào): V62C1804096
廠商: Mosel Vitelic, Corp.
英文描述: LCD Displays 6.4 inch (16.0 cm) 18-bit digital (6 bits/color)
中文描述: 為512k × 8,的CMOS靜態(tài)RAM
文件頁(yè)數(shù): 2/10頁(yè)
文件大小: 157K
代理商: V62C1804096
2
V62C1804096 Rev. 1.0 October 2001
MOSEL VITELIC
V62C1804096
Pin Descriptions
A
0
–A
18
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
Address Inputs
CE
1
, CE
2
Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
Output Enable Input
WE
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
Write Enable Input
I/O
1
–I/O
8
These 8 bidirectional ports are used to read data
from and write data into the RAM.
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
36 BGA
A
1
2
3
4
5
6
1
Note:
NC means no connect.
NB means no ball.
2
TOP VIEW
TOP VIEW
3
4
5
6
B
C
D
E
F
G
H
A
A0
I/O5
I/O6
B
C
D
E
F
G
H
VSS
VCC
I/O7
I/O8
A9
A1
A2
NB
NB
NB
NB
OE
A10
CE2
WE
NC
NB
NB
A18
CE1
A11
A3
A4
A5
NB
NB
A17
A16
A12
A6
A7
NB
NB
NB
NB
A15
A13
A8
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
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