參數(shù)資料
型號(hào): V62C1802048LL-85V
廠商: Mosel Vitelic, Corp.
英文描述: LCD Displays 5.0 inch (13.0 cm) Comp NTSC
中文描述: 超低功耗256K × 8 CMOS SRAM的
文件頁(yè)數(shù): 1/9頁(yè)
文件大小: 84K
代理商: V62C1802048LL-85V
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
A
8
A
13
WE
CE
2
A
15
Vcc
A17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
9
A
11
32
31
30
29
28
27
26
25
24
23
17
18
19
20
21
22
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
A
10
OE
Cell Array
R
S
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
A
8
A9
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
V 62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10
μ
A
(CMOS input/output)
2
μ
A
CMOS input/output, L version
Single + 1.8 to 2.2V Power Supply
Equal access and cycle time
70/85/100/150 ns access time
Easy memory expansion with CE1, CE2
and OE inputs
1.0V data retention mode
TTL compatible, Tri-state input/output
Automatic power-down when deselected
Package available: 32-TSOP1 / STSOP
Functional Description
The V62C1802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1, an active HIGH CE2, an act-
ive LOW OE, and Tri-state I/O’s. This device has an auto-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1) with Write Enable (WE) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
32-Pin TSOP1 / STSOP
Logic Block Diagram
REV. 1.
2
May
2001 V62C
18020
48
L(L)
1
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