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參數(shù)資料
| 型號(hào)： | V62C1164096 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | LCD Displays 12.1 inch (31.0 cm) LVDS |
| 中文描述： | 256K × 16，的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 178K |
| 代理商： | V62C1164096 |
2
V62C1164096 Rev. 1.0 November 2001
MOSEL VITELIC
V62C1164096
Pin Descriptions
A
0
–A
17
These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
Address Inputs
CE
1
, CE
2
Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
The output enable input is active LOW. With the
chip enabled, when OE is Low and WE High, data
will be presented on the I/O pins. The I/O pins will
be in the high impedance state when OE is High.
Output Enable Input
UBE, LBE
Active low inputs. These inputs are used to enable
the upper or lower data byte.
Byte Enable
WE
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
Write Enable Input
I/O
1
–I/O
16
These 16 bidirectional ports are used to read data
from and write data into the RAM.
Data Input and Data Output Ports
V
CC
GND
Power Supply
Ground
Pin Configurations (Top View)
48 BGA
A
1
2
3
4
5
6
1
Note:
NC means no connect.
2
3
4
5
6
B
C
D
E
F
G
H
TOP VIEW
TOP VIEW
A
BLE
I/O9
I/O10
B
C
D
E
F
G
H
VSS
VCC
I/O15
I/O16
NC
OE
BHE
I/O11
I/O12
I/O13
I/O14
NC
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
1
I/O2
I/O4
I/O5
I/O6
WE
A11
CE
2
I/O1
I/O3
VCC
VSS
I/O7
I/O8
NC
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