參數(shù)資料
型號(hào)： V59C1G01804QALF25A
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù)： 21/79頁(yè)
文件大?。?/td> 1028K
代理商： V59C1G01804QALF25A
28
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the
start of the command until the data from the first cell appears on the outputs is equal to the value of the read
latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto
the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each sub-
sequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The
RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set
(MRS). The AL is defined by the Extended Mode Register Set (EMRS).
Basic Burst Read Timing
CK, CK
DQS,
DQS
DQ
CK
DQS
t CH
t CL
t RPRE
t DQSQmax
t QH
t
RPST
DQSQmax
t
QH
t
DO
don’t care
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T8
Dout A0
Dout A1
Dout A2
Dout A3
RL = 5
AL = 2
CL = 3
NOP
<= tDQSCK
CMD
DQ
BRead523
DQS,
DQS
Post CAS
CK, CK
相關(guān)PDF資料
PDF描述
V59C1G01804QAUJ19AH 128M X 8 DDR DRAM, PBGA68
V59C1G01804QAUJ25AI 128M X 8 DDR DRAM, PBGA68
V59C1G01808QALF19E 128M X 8 DDR DRAM, BGA68
V59C1G01808QALF37E 128M X 8 DDR DRAM, BGA68
V59C1G01808QAUF37H 128M X 8 DDR DRAM, PBGA68
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