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參數(shù)資料
| 型號： | V59C1512168QAUJ25 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, PBGA92 |
| 封裝： | GREEN, FBGA-92 |
| 文件頁數(shù)： | 51/79頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | V59C1512168QAUJ25 |
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55
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Self Refresh Exit
L
H
HX
X
1,7,8
LH
H
Single Bank Precharge
H
L
H
L
BA
X
L
X
1,2
Precharge all Banks
H
L
H
L
X
H
X
1
Bank Activate
H
L
H
BA
Row Address
1,2
Write
H
L
H
L
BA
Column
L
Column
1,2,3,
Write with Auto Precharge
H
L
H
L
BA
Column
H
Column
1,2,3,
Read
H
L
H
L
H
BA
Column
L
Column
1,2,3
Read with Auto-Precharge
H
L
H
L
H
BA
Column
H
Column
1,2,3
No Operation
H
X
L
H
X
1
Device Deselect
H
X
H
X
1
Power Down Entry
H
L
HX
X
XX
X
1,4
LH
H
Power Down Exit
L
H
HX
X
XX
X
1,4
LH
H
NOTE 1
All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
NOTE 2
Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an
(Extended) Mode Register.
NOTE 3
Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and
"Writes interrupted by a Write" in section 2.6 for details.
NOTE 4
The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the
refresh requirements outlined in section 2.9.
NOTE 5
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
See section 2.4.4.
NOTE 6
“X” means “H or L (but a defined logic level)”
NOTE 7
Self refresh exit is asynchronous.
NOTE 8
VREF must be maintained during Self Refresh operation.
NOTE 9
BAx and Axx refers to the MSBs of bank addresses and addresses, respectively, per device density.
Function
CKE
CS
RAS
CAS
WE
BA0
-
BAx9
Axx9-A11 A10
A9 - A0
Notes
Previous
Cycle
Current
Cycle
Command Truth Table
(Extended) Mode Register Set
H
L
BA
OP Code
1,2
Refresh (REF)
H
L
H
X
1
Self Refresh Entry
H
L
H
X
1,8
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