參數(shù)資料
型號(hào): V59C1512164QAUP19AH
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, PBGA92
封裝: GREEN, FBGA-92
文件頁數(shù): 50/79頁
文件大?。?/td> 1028K
代理商: V59C1512164QAUP19AH
54
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE
asynchronously drops “l(fā)ow” during any valid operation DRAM is not guaranteed to preserve the contents of
the memory array. If this event occurs, the memory controller must satisfy a time delay ( tdelay ) before turn-
ing off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised “high” again. The
DRAM must be fully re-initialized as described the the initialization sequence starting with step 4.
The DRAM is ready for normal operation after the initialization sequence. The minimum time clocks needs
to be ON after CKE asynchronously drops low (the tdelay timing parameter) is equal to tIS + tCK + tIH.
Asynchronous CKE Low Event
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
tdelay
CK, CK
stable clocks
相關(guān)PDF資料
PDF描述
V59C1512168QALP25E 32M X 16 DDR DRAM, BGA92
V59C1512168QAUF37I 32M X 16 DDR DRAM, PBGA92
V59C1512168QAUJ19H 32M X 16 DDR DRAM, PBGA92
V59C1512168QAUJ25 32M X 16 DDR DRAM, PBGA92
V59C1G01408QAUP5E 256M X 4 DDR DRAM, BGA68
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