參數(shù)資料
型號： V58C2256404SHLB6I
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, PBGA60
封裝： M0-233, BGA-60
文件頁數(shù)： 13/60頁
文件大?。?/td> 1125K
代理商： V58C2256404SHLB6I
20
V58C2256(804/404/164)SH Rev. 1.1 July 2010
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
Burst Write Timing
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
WRITE
NOP
D0
D1
D2
D3
CK, CK
Command
DQS(nom)
DQ(nom)
tWPRES
tDQSS
tWPST
tDH
D0
D1
D2
D3
DQS(min)
DQ(min)
tDQSS(min)
D0
D1
D2
D3
DQS(max)
DQ(max)
tWPRES(min)
tDQSS(max)
tDS
tDH
tWPRES
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