參數(shù)資料
型號： V54C3256164VBUT
廠商： Mosel Vitelic, Corp.
英文描述： LOW POWER 256Mbit SDRAM 3.3 VOLT, 54-BALL SOC BGA 54-PIN TSOPII 16M X 16
中文描述： 低功耗的256Mbit SDRAM的3.3伏，54球的BGA SOC的54引腳TSOPII 16米x 16
文件頁數(shù)： 1/45頁
文件大小： 651K
代理商： V54C3256164VBUT
MOSEL VITELIC
1
V54C3256164VBUC/T
LOW POWER 256Mbit SDRAM
3.3 VOLT, 54-BALL SOC BGA
54-PIN TSOPII 16M X 16
V54C3256164VBUC/T Rev. 1.1 February 2003
PRELIMINARY
6
7PC
7
8PC
System Frequency (f
CK
)
166 MHz
143 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
7 ns
8 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
5.4 ns
6 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.4 ns
5.4 ns
6 ns
6 ns
Features
■
4 banks x 4Mbit x 16 organization
■
High speed data transfer rates up to 166 MHz
■
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■
Single Pulsed RAS Interface
■
Data Mask for Read/Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 3
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
■
Multiple Burst Read with Single Write Operation
■
Automatic and Controlled Precharge Command
■
Random Column Address every CLK (1-N Rule)
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 54-Ball SOC BGA/ 54-Pin TSOP II
■
LVTTL Interface
■
Single +3.3 V
±
0.3 V Power Supply
■
Low Power Self Refresh Current
■
L-version 1.0mA
■
U-version 0.6mA
Description
The V54C3256164VBUC/T is a low power four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16. The V54C3256164VBUC/T achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
The V54C3256164VBUC/T is ideally suited for
high performance, low power systems such as
PDA, mobile phone, DSC, and other battery backup
applications.
Device Usage Chart
Operating
Temperature
Range
Package Out-
line
Access Time (ns)
Power
Temperature
Mark
C/T
6
7PC
7
8PC
Std.
L
U
T
0
°
C to 70
°
C
Blank
相關(guān)PDF資料
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V54C3256404VB 256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V54C3256164VS 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256164VT 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256404VAB 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256404VAT 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256404VB 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
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