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參數資料
| 型號： | V54C316162VC-5 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| 中文描述： | 200/183/166/143 MHz的3.3伏和2K刷新超高性能100萬× 16 SDRAM的2組X 512Kbit × 16 |
| 文件頁數： | 7/21頁 |
| 文件大小： | 322K |
| 代理商： | V54C316162VC-5 |
7
V54C316162V Rev. 2.9 September 2001
MOSEL VITELIC
V54C316162V
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one t
RC
delay
is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“
high
”
at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t
DQZ
). It also provides
a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
ited (DQM Write Mask Latency t
DQW
= zero clocks).
DQM is used for device selection, byte selection
and bus control in a memory system. LDQM con-
trols DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Suspend Mode
During normal access mode, CKE is held high en-
abling the clock. When CKE is low, it freezes the in-
ternal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t
CSL
).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can
’
t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE
“
high
”
. One clock delay is required for
mode entry and exit.
Auto Precharge
Two
methods
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, A
10
, to de-
termine whether the chip restores or not after the
operation. If A
10
is high when a Read Command is
issued, the
Read with Auto-Precharge
function is
initiated. The SDRAM automatically enters the pre-
charge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3.
If A
10
is high when a Write Command is issued, the
Write with Auto-Precharge
function is initiated.
The SDRAM automatically enters the precharge op-
eration a time delay equal to t
WR
(Write recovery
time) after the last data in.
are
available
to
precharge
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge op-
eration. With A
10
being low, the BA is used select
bank to precharge. The precharge command can be
imposed one clock before the last data out for CAS
latency = 2, two clocks before the last data out for
CAS latency = 3. Writes require a time delay twr
from the last data out to apply the precharge com-
mand. If A
10
is high, all banks will be precharged.
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate
the
burst
operation
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
prematurely.
These
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