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參數(shù)資料
| 型號： | V54C3128804VAT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 |
| 中文描述： | 高性能143/133/125MHz 3.3伏16米x 8同步DRAM 4銀行X的4Mb × 8 |
| 文件頁數(shù)： | 1/43頁 |
| 文件大?。?/td> | 362K |
| 代理商： | V54C3128804VAT |
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MOSEL VITELIC
1
V54C3128804VAT
HIGH PERFORMANCE 143/133/125MHz
3.3 VOLT 16M X 8 SYNCHRONOUS DRAM
4 BANKS X 4Mbit X 8
V54C3128804VAT Rev. 1.4 November 2000
PRELIMINARY
7PC
7
8PC
System Frequency (f
CK
)
143 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
7 ns
7 ns
8 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
6 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.4 ns
6 ns
6 ns
Features
I
4 banks x 4Mbit x 8 organization
I
High speed data transfer rates up to 143 MHz
I
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
I
Single Pulsed RAS Interface
I
Data Mask for Read/Write Control
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 2, 3
I
Programmable Wrap Sequence: Sequential or
Interleave
I
Programmable Burst Length:
1, 2, 4, 8 and Sequential Type
1, 2, 4, 8 for Interleave Type
I
Multiple Burst Read with Single Write Operation
I
Automatic and Controlled Precharge Command
I
Random Column Address every CLK (1-N Rule)
I
Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 54 Pin 400 mil TSOP-II
I
LVTTL Interface
I
Single +3.3 V
±
0.3 V Power Supply
Description
The V54C3128804VAT is a four bank Synchro-
nous DRAM organized as 4 banks x 4Mbit x 8. The
V54C3128804VAT achieves high speed data trans-
fer rates up to 143 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
7PC
7
8PC
Std.
L
0
°
C to 70
°
C
Blank
相關(guān)PDF資料 |
PDF描述 |
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| V54C316162VB | High Performance 3.3 Volt 1M X 16 Synchronous DRAM(3.3V高性能1Mx16同步動態(tài)RAM) |
| V54C316162 | 200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-5 | 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-55 | 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-6 | 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C3128804VAT7 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 |
| V54C3128804VAT8 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 |
| V54C3128804VBGA | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, BGA PACKAGE |
| V54C3128804VBJ7IPC | 制造商:Mosel Vitelic Corporation 功能描述: |
| V54C3128804VS | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
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