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參數(shù)資料
| 型號： | V53C8125H40 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | ULTRA-HIGH PERFORMANCE, 128K X 8 FAST PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 超高性能，128K的乘八快速頁面模式的CMOS動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 1527K |
| 代理商： | V53C8125H40 |
14
MOSEL VITELIC
V53C8125H
V53C8125H Rev. 1.7 August 1998
Functional Description
The V53C8125H is a CMOS dynamic RAM opti-
mized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C8125H reads and writes
data by multiplexing an 17-bit address into a 8-bit
row and an 9-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address ìflows through an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
ed or aborted before the minimum tRAS time has ex-
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
mum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Refresh Cycle
To retain data, 256 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1.
By clocking each of the 512 row addresses (A0
through A8) with RAS at least once every 8 ms.
Any Read, Write, Read-Modify-Write or RAS-
only cycle refreshes the addressed row.
2.
Using a CAS-before-RAS Refresh Cycle. If
CAS makes a transition from low to high to low
after the previous cycle and before RAS falls,
CAS-before-RAS refresh is activated. The
V53C8125H uses the output of an internal 9-bit
counter as the source of row addresses and ig-
nore external address inputs.
CAS-before-RAS is a ìrefresh-only mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cy-
cle. A CAS-before-RAS counter test mode is provid-
ed to ensure reliable operation of the internal
refresh counter.
Fast Page Mode Operation
Fast Page Mode operation permits all 256 col-
umns within a selected row of the device to be ran-
domly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column ad-
dress buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode opera-
tion, Read, Write, Read-Modify-Write or Read-
Write-Read cycles are possible at random address-
es within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
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